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ORCIDHidehiro Fujiwara
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2020 – today
- 2024
[j15]Xiaoyu Sun
, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang:
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1191-1205 (2024)- [c30]Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, Ming-Hung Lin, Pei-Kuei Tsung, En-Jui Chang, Jenwei Liang, Shu-Hsin Chang, Chung-Lun Huang, You-Yu Nian, Zhe Wan, Sushil Kumar, Cheng-Xin Xue, Gajanan Jedhe, Hidehiro Fujiwara, Haruki Mori, Chih-Wei Chen, Po-Hua Huang, Chih-Feng Juan, Chung-Yi Chen, Tsung-Yao Lin, Ch Wang, Chih-Cheng Chen, Kevin Jou:
20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices. ISSCC 2024: 360-362 - [c29]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC 2024: 572-574 - [c28]Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c27]Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. ISSCC 2023: 132-133 - [c26]Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li:
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. VLSI Technology and Circuits 2023: 1-2 - [c25]Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c24]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. ISSCC 2022: 1-3 - [c23]Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. VLSI Technology and Circuits 2022: 24-25 - 2021
- [j14]Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. IEEE J. Solid State Circuits 56(1): 179-187 (2021) - [c22]Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang:
An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. ISSCC 2021: 252-254 - [c21]Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang:
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. ISSCC 2021: 340-342 - 2020
- [c20]Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. ISSCC 2020: 238-240
2010 – 2019
- 2019
- [c19]Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang:
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. ISSCC 2019: 390-392 - 2018
- [j13]Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Tanaka, Koji Nii:
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2335-2344 (2018) - 2017
- [c18]Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu:
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. ISSCC 2017: 206-207 - 2016
- [c17]Hidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Rung Wu, Hung-Jen Liao, Jonathan Chang:
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications. A-SSCC 2016: 185-188 - 2015
- [c16]Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang:
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. ISSCC 2015: 1-3 - 2014
- [j12]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [c15]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - [c14]Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii:
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. ISQED 2014: 523-528 - 2013
- [c13]Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii:
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. CICC 2013: 1-4 - [c12]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda:
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED 2013: 438-441 - 2012
- [j11]Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto:
Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Trans. Commun. 95-B(1): 178-188 (2012) - [j10]Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. 95-C(4): 579-585 (2012) - [c11]Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto:
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. Asian Test Symposium 2012: 246-251 - [c10]Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu:
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED 2012: 270-274 - [c9]Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki:
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238 - [c8]Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii:
A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC 2012: 143-147 - 2011
- [j9]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6(2): 296-306 (2011) - [j8]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4: 80-90 (2011) - [j7]Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa:
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. IEEE J. Solid State Circuits 46(11): 2535-2544 (2011) - [c7]Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii:
A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED 2011: 285-290 - 2010
- [c6]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524
2000 – 2009
- 2009
- [j6]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. 92-C(4): 423-432 (2009) - [c5]Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663 - [c4]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300 - 2008
- [j5]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. 91-C(4): 543-552 (2008) - [j4]Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 620-627 (2008) - [c3]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102 - 2007
- [j3]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Trans. Electron. 90-C(10): 1949-1956 (2007) - [j2]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2695-2702 (2007) - [c2]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112 - 2006
- [j1]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006) - [c1]Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
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