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  • Delhi, Delhi, India

Rakhi Narang

Du, Electronics, Department Member
The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device... more
The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device performance due to the rise in temperature has also been investigated for the case of Silicon DG-MOSFET and a comparison with DG-TFET is made. The parameters governing the analog performance and linearity has been studied and the impact of a gate stack (GS) architecture has also been investigated for the same.
Research Interests:
This work presents a study on Double gate Tunnel Field effect transistor (DG-TFET) with a multi layer gate dielectric, commonly known as Gate Stack (GS) architecture. An analytical model has been developed to obtain compact analytical... more
This work presents a study on Double gate Tunnel Field effect transistor (DG-TFET) with a multi layer gate dielectric, commonly known as Gate Stack (GS) architecture. An analytical model has been developed to obtain compact analytical expressions for various parameters like electron concentration in the channel, energy bands, potential and electric field at the tunneling junction. Band to band tunneling generation rate and tunneling probability has been evaluated. The performance of gate stack DG-TFET in terms of high drive current is shown through device simulation. The results obtained from analytical expressions are compared with device simulator results.
.in Abstract- Nanowire MOSFETs have been recognized as one of the possible choices to continue the scaling of CMOS beyond conventional scaling limits. In present study we study various aspects of device characteristics and Mixedmode... more
.in Abstract- Nanowire MOSFETs have been recognized as one of the possible choices to continue the scaling of CMOS beyond conventional scaling limits. In present study we study various aspects of device characteristics and Mixedmode circuit behavior of Silicon and Germanium Nanowire MOSFETs. The various parameters determining the behavior of device in the analog/digital circuits is studied and compared for
In this letter, we propose a dielectric modulated double-gate tunnel field-effect transistor (DG-TFET)-based sensor for low power consumption label-free biomolecule detection applications. A nanogap-embedded FET-based biosensor has... more
In this letter, we propose a dielectric modulated double-gate tunnel field-effect transistor (DG-TFET)-based sensor for low power consumption label-free biomolecule detection applications. A nanogap-embedded FET-based biosensor has already been demonstrated experimentally, but a TFET-based biosensor has not been demonstrated earlier. Thus, a concept of TFET-based sensor is presented by analytical and simulation-based study. The results indicate better sensitivity toward two different effects (dielectric constant and charge of biomolecule) in comparison with a FET-based biosensor, and the additional advantages of CMOS compatibility, low leakage (low static power dissipation), and steep subthreshold slope make TFET an attractive alternative architecture for CMOS-based sensor applications.
This work presents the performance evaluation of an asymmetric gate oxide Double Gate Tunnel Field Effect Transistor (DG-TFET) based on the concept of Heterogeneous Dielectric with a high-k material at the source side and low-k at the... more
This work presents the performance evaluation of an asymmetric gate oxide Double Gate Tunnel Field Effect Transistor (DG-TFET) based on the concept of Heterogeneous Dielectric with a high-k material at the source side and low-k at the drain end. But, in order to improve the performance further, the low-k oxide material (SiO2) at the drain end is replaced with air (k=1) to alleviate the problem of high gate drain capacitance, thus providing improved cut-off frequency, circuit performance in terms of inverter propagation delay and suppressed ambipolar behavior.