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This paper describes two novel algorithms based on the time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow ...

This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow ...

This paper reports an evaluation of adapted digital signals as a test stimulus to test dynamic parameters of analog-to-digital converters (ADC). In the first instance, the simplest digital waveform, a pulse signal, is taken as the test stimulus. The ...

This article describes an analog test bus infrastructure as a straightforward approach to grant the accessibility to embedded RF or Analog modules in core-based design. This DfT method increases the testability and provides debug/diagnosis facilities. ...

Application specific ICs are typically designed to meet a given performance specification. For these ICs a higher performance does not add value and less performance makes the IC useless. This class of ICs is designed based on worst-case corner ...

Excessive power supply noise can affect path delay in ICs. Silicon results show that filling of don't-care bits in test patterns can cause as much as 15% delay variation. Such extra delay may cause overkill during delay test. This article describes two ...

AC sensitivities guide most Analogue Automatic Test Pattern Generator (AATPG) while determining the optimal frequencies of a sinusoidal test stimulus. The optimal frequencies thus determined, normally lie in the close vicinity of the operating frequency ...

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit's DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty ...

The paper addresses the issue of transistor-level bridging fault diagnosis. While most of the previous bridging fault diagnosis work focuses on the gate-level bridging faults, this method provides a solution to intragate bridging faults diagnosis for ...

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, ...

While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the transistor level. The stuck-open fault is one of them. In this paper we introduce a stuck-open fault diagnosis method based on the stuck-at ...

Resistive bridges not only cause a static faulty behavior in CMOS memories, but also lead to several dynamic faulty behaviors which are timing related failures. This paper introduces a new realistic dynamic fault model for random access-memories: the ...

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low ...

An innovative approach for testing PLLs in open loopmode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected ...

This paper proposes an effective method for applying finedelay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. ...

Circuits are tested for both functionality and performance. As opposed to circuits with large delay faults, circuits with small delay faults are difficult to diagnose and as such are potential test escapes. This paper presents a strategy to diagnose ...

The known methods of transition fault diagnosis usually sufferfrom the drawback of many candidates. The method presentedin this paper aims at reducing the number of suspects. The transitionfault patterns were generated by Philips in-house ATPGtool and ...

A crucial issue for using defect-oriented testing in analogue testing is how to reduce the massive fault- simulation time. One solution to this problem is to use high-level models in the fault simulation. However, the high-level model used in fault ...

This paper reflects on some recent results that show thevalue of delay-fault tests on a deep sub-micron process.However, the results also suggest that untargetted testpatterns perform almost as well as those targetted on atransition fault model, despite ...

This defect-based study analyzes statisticalsignal delay properties and delay fault test patternconstraints in the CMOS deep submicron environment.Delay fault testing has uncertainty, or noise, in its attemptto detect defects that slow a signal.CMOS ...