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- research-articleJuly 2024
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance
Expert Systems with Applications: An International Journal (EXWA), Volume 249, Issue PCSep 2024https://doi.org/10.1016/j.eswa.2024.123828AbstractIn vehicular accidents, the swift and accurate identification of car crashes is paramount, as it serves as the linchpin for prompt responses from emergency services and search-and-rescue operations. This study introduces an innovative multimodal ...
Highlights- Introduction of a Novel Audio-Visual Fusion Approach.
- Multimodal Processing-Based Vehicle Collision Detection System.
- Utilization of RGB, Optical Flow, and Difference Processing for Video Data.
- Inference Applicable to Testing ...
- research-articleApril 2024
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferenceJanuary 2024, Pages 225–230https://doi.org/10.1109/ASP-DAC58780.2024.10473883With the rapid explosion in both graph scale and model size, accelerating graph neural networks (GNNs) at scale encounters significant pressure on computation and memory footprint. Exploiting data sparsity with pruning, which exhibits remarkable effect ...
- research-articleApril 2024
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in near Data Processing with Bridge Architecture
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferenceJanuary 2024, Pages 460–465https://doi.org/10.1109/ASP-DAC58780.2024.10473860Near data accelerators (NDAs) enable near data processing (NDP) within main memory that benefits performance by providing more aggregated bandwidth and reducing longdistance data transfer. Most prior works focus on reaping higher internal bandwidth to ...
- ArticleDecember 2023
RTMDet-R2: An Improved Real-Time Rotated Object Detector
Pattern Recognition and Computer VisionOct 2023, Pages 352–364https://doi.org/10.1007/978-981-99-8555-5_28AbstractObject detection in remote sensing images is challenging due to the absence of visible features and variations in object orientation. Efficient detection of objects in such images can be achieved using rotated object detectors that utilize ...
- research-articleSeptember 2023
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 9Sept. 2023, Pages 3078–3091https://doi.org/10.1109/TCAD.2023.3238292With the increasing of dynamic random access memory’s (DRAM) capacity, the refresh operation rapidly becomes a major concern to the performance of the current computational system. Moreover, conservative timing parameters adopted for access ...
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- research-articleJuly 2023
3<italic>A</italic>-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 1Jan. 2024, Pages 176–188https://doi.org/10.1109/TCAD.2023.3297968ReRAM-based computing is good at accelerating convolutional neural network (CNN) inference due to its high computing parallelism, but its rigid crossbar structure may become less efficient in the face of the random data sparsity abundant in CNNs. In this ...
- research-articleMarch 2023
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 3March 2023, Pages 874–886https://doi.org/10.1109/TCAD.2022.3185544When a coarse-grained reconfigurable array (CGRA) architecture shifts toward cross-domain acceleration, control flow and memory accesses often degrade the processing elements (PEs) utilization and array efficiency by breaking the intact dataflow graph (...
- research-articleJanuary 2023
An Efficient near-Bank Processing Architecture for Personalized Recommendation System
ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation ConferenceJanuary 2023, Pages 122–127https://doi.org/10.1145/3566097.3567857Personalized recommendation systems consume the major resources in modern AI data centers. The memory-bound embedding layers with irregular memory access patterns have been identified as the bottleneck of recommendation systems. To overcome the memory ...
- research-articleNovember 2022
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 27, Issue 6Article No.: 57, Pages 1–22https://doi.org/10.1145/3510819Resistive-RAM-based (ReRAM-based) computing shows great potential on accelerating DNN inference by its highly parallel structure. Regrettably, computing accuracy in practical is much lower than expected due to the non-ideal ReRAM device. Conventional ...
- research-articleDecember 2021
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement
2021 58th ACM/IEEE Design Automation Conference (DAC)Dec 2021, Pages 1093–1098https://doi.org/10.1109/DAC18074.2021.9586146As the capacity of DRAM continues to grow, the refresh operation rapidly becomes the performance and power-efficiency bottleneck. Also, restore time, the time given for recharging cells post access, makes an increasingly large amount of negative impact on ...
- research-articleFebruary 2021
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing
- Zhuojun Liang,
- Dongxu Lv,
- Chao Cui,
- Hai-Bao Chen,
- Weifeng He,
- Weiguang Sheng,
- Naifeng Jing,
- Zhigang Mao,
- Guanghui He
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 29, Issue 2Feb. 2021, Pages 307–320https://doi.org/10.1109/TVLSI.2020.3036822This article presents an <inline-formula> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> lattice-reduction-aided (LRA) soft-output multiple-input multiple-output (MIMO) detector for Chinese enhanced ultrahigh throughput (EUHT) ...
- research-articleSeptember 2020
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSISeptember 2020, Pages 345–350https://doi.org/10.1145/3386263.3406915The Resistive-RAM (RRAM) based deep neural network (DNN) accelerators have shown great potential as they are good at solving matrix-vector multiplication (MVM). However, this computing paradigm does not benefit other NN operations like activation, which ...
- research-articleMarch 2019
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 2Article No.: 25, Pages 1–22https://doi.org/10.1145/3306495The coming era of big data revives the Processing-in-memory (PIM) architecture to relieve the memory wall problem that embarrasses the modern computing system. However, most existing PIM designs just put computing units closer to memory, rather than a ...
- research-articleSeptember 2017
A 12-bit 4928 3264 pixel CMOS image signal processor for digital still cameras
Integration, the VLSI Journal (INTG), Volume 59, Issue CSeptember 2017, Pages 206–217https://doi.org/10.1016/j.vlsi.2017.06.005In this paper a 4928 3264 pixel CMOS image signal processor (ISP) is proposed for digital still cameras with low complexity and high performance. To reduce hardware cost and keep high performance, novel algorithms are proposed to process image signals. ...
- research-articleSeptember 2017
Dynamic data split
Integration, the VLSI Journal (INTG), Volume 59, Issue CSeptember 2017, Pages 23–30https://doi.org/10.1016/j.vlsi.2017.04.003Through-silicon via (TSV) technology improves transmission bandwidth in three-dimensional integrated circuits (3D ICs) due to its short connection path. However, it is limited by crosstalk issues, especially in closely spaced TSV clusters. The present ...
- research-articleMay 2017
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 5May 2017, Pages 1593–1600https://doi.org/10.1109/TVLSI.2016.2645282In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification ...
- research-articleApril 2017
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic
Microelectronics Journal (MICROJ), Volume 62, Issue CApril 2017, Pages 12–20https://doi.org/10.1016/j.mejo.2017.01.010A new variable strength keeper technique is proposed in this paper for achieving robust, high-speed, and low-leakage dynamic logic gates with carbon nanotube transistors. The strength of keeper is dynamically adjusted depending on the logical state of ...
- research-articleMarch 2017
A static-placement, dynamic-issue framework for CGRA loop accelerator
DATE '17: Proceedings of the Conference on Design, Automation & Test in EuropeMarch 2017, Pages 1348–1353This paper presents a static-placement, dynamic-issue (SPDI) framework for the coarse-grained reconfigurable architecture (CGRA) in order to tackle the inefficiencies of the static-issue, static-placement (SISP) CGRA. This framework includes the ...
- research-articleMarch 2017
<italic>In Situ</italic> Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 25, Issue 3March 2017, Pages 1032–1043https://doi.org/10.1109/TVLSI.2016.2625598In order to achieve high tolerance against process, voltage, and temperature variations in the ultralow voltage (ULV) circuits, in situ error detection and correction (EDAC) techniques were presented. However, circuits adding the capability of error ...
- research-articleJanuary 2017
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)Jan 2017, Pages 87–92https://doi.org/10.1109/ASPDAC.2017.7858301In this paper, the effect of negative bias temperature instability (NBTI) on MBUs sensitivity of 65 nm bulk technology memories is analyzed and simulated by Geant4. A MTTF reliability model including NBTI stress time is proposed for memories protected by ...