Article

Vectorless Analysis of Supply Noise Induced Delay Variation

Authors:

Vladimir Zolotov,

Savithri Sundareswaran,

Rajendran PandaAuthors Info & Claims

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Page 184

Published: 09 November 2003 Publication History

Abstract

The impact of power supply integrity on a design has become acritical issue, not only for functional verification, but also for performanceverification. Traditional analysis has typically applied a worstcase voltage drop at all points along a circuit path which leads to avery conservative analysis. We also show that in certain cases, thetraditional analysis can be optimistic, since it ignores the possibilityof voltage shifts between driver and receiver gates. In this paper, wepropose a new analysis approach for computing the maximum pathdelay under power supply fluctuations. Our analysis is based on theuse of superposition, both spatially across different circuit blocks,and temporally in time. We first present an accurate model of pathdelay variations under supply drops, considering both the effect oflocal supply reduction at individual gates and voltage shifts betweendriver/receiver pairs. We then formulate the path delay maximizationproblem as a constrained linear optimization problem, consideringthe effect of both IR drop and LdI/dt drops. We show how correlationsbetween currents of different circuit blocks can be incorporatedin this formulation using linear constraints. The proposed methodswere implemented and tested on benchmark circuits, including anindustrial power supply grid and we demonstrate a significantimprovement in the worst-case path delay increase.

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Cited By

Okumura TMinami FShimazaki KKuwada KHashimoto MLin Y(2010)Gate delay estimation in STA under dynamic power supply noiseProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899899(775-780)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899899
Tao YLim SBenini LDe Micheli GAl-Hashimi BMueller W(2009)Decoupling capacitor planning with analytical delay model on RLC power gridProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874825(839-844)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874825
Chen HChang CHwang T(2009)New spare cell design for IR drop minimization in Engineering Change OrderProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630017(402-407)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630017
Show More Cited By

Index Terms

Vectorless Analysis of Supply Noise Induced Delay Variation
1. Hardware

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Information

Published In

cover image ACM Conferences

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

November 2003

899 pages

ISBN:1581137621

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 09 November 2003

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Article

Conference

ICCAD03

Sponsor:

SIGDA

ICCAD03: The International Conference on Computer-Aided Design

November 9 - 13, 2003

Acceptance Rates

ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Okumura TMinami FShimazaki KKuwada KHashimoto MLin Y(2010)Gate delay estimation in STA under dynamic power supply noiseProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899899(775-780)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899899
Tao YLim SBenini LDe Micheli GAl-Hashimi BMueller W(2009)Decoupling capacitor planning with analytical delay model on RLC power gridProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874825(839-844)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874825
Chen HChang CHwang T(2009)New spare cell design for IR drop minimization in Engineering Change OrderProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630017(402-407)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630017
Chen PLiu CHwang TNassif SRoychowdhury J(2008)Transition-aware decoupling-capacitor allocation in power noise reductionProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509555(426-429)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509555
Wang JWalker DLu XMajhi AKruseman BGronthoud GVillagra Lvan de Wiel PEichenberger S(2007)Modeling Power Supply Noise in Delay TestingIEEE Design & Test10.1109/MDT.2007.7624:3(226-234)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1109/MDT.2007.76
Hashimoto MYamaguchi JOnodera H(2007)Timing Analysis Considering Spatial Power/Ground Level VariationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.12.2661E90-A:12(2661-2668)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1093/ietfec/e90-a.12.2661
Pant SBlaauw D(2005)Static timing analysis considering power supply variationsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129655(365-371)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129655
Hashimoto MYamaguchi JSato TOnodera HTang T(2005)Timing analysis considering temporal supply voltage fluctuationProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120833(1098-1101)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120833
Shao MGao YYuan LWong M(2005)IR Drop and Ground Bounce Awareness Timing ModelProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.44(226-231)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.44
Graziano MForzan CPandini D(2005)Power supply selective mapping for accurate timing analysisProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_28(267-276)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_28
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