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Getting to the bottom of deep submicron

Authors:

Dennis Sylvester,

Kurt KeutzerAuthors Info & Claims

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Pages 203 - 211

https://doi.org/10.1145/288548.288614

Published: 01 November 1998 Publication History

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Cited By

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Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Pagliarini SIsgenc MMartins MPileggi L(2018)Application and Product-Volume-Specific Customization of BEOL Metal PitchIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282838726:9(1627-1636)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2828387
Kahng AKahng ALee HLi J(2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
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Index Terms

Getting to the bottom of deep submicron
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Semiconductor memory
  2. Robustness

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ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

November 1998

704 pages

ISBN:1581130082

DOI:10.1145/288548

Chairman:
Hiroto Yasuura
Kyushu Univ., Fukuoka, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 November 1998

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ICCAD '98: International Conference on Computer-Aided Design - 1998

November 8 - 12, 1998

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Madhavan SPhadke RN B(2021)Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System2021 International Conference on Circuits, Controls and Communications (CCUBE)10.1109/CCUBE53681.2021.9702732(1-6)Online publication date: 23-Dec-2021
https://doi.org/10.1109/CCUBE53681.2021.9702732
Pagliarini SIsgenc MMartins MPileggi L(2018)Application and Product-Volume-Specific Customization of BEOL Metal PitchIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282838726:9(1627-1636)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2828387
Kahng AKahng ALee HLi J(2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
https://doi.org/10.1109/TCAD.2017.2750072
Rukkumani VDevarajan N(2016)Design and analysis of an Amplifier circuit using Micron Technology2016 IEEE Region 10 Conference (TENCON)10.1109/TENCON.2016.7848605(3039-3044)Online publication date: Nov-2016
https://doi.org/10.1109/TENCON.2016.7848605
Kahng ALee HLi JCavallaro JZhang TJones ALi H(2014)Horizontal benchmark extension for improved assessment of physical CAD researchProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591540(27-32)Online publication date: 20-May-2014
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Moiseev KKolodny AWimer SMoiseev KKolodny AWimer S(2014)Net-by-Net Wire OptimizationMulti-Net Optimization of VLSI Interconnect10.1007/978-1-4614-0821-5_5(43-61)Online publication date: 16-Oct-2014
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Zarei MAsadpour RMohammadi SAfzali-Kusha ASeyyedi RAyala JJones AMadden PCoskun A(2013)Modeling symmetrical independent gate FinFET using predictive technology modelProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483114(299-304)Online publication date: 2-May-2013
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Xu TSchley GLiljeberg PRadetzki MPlosila JTenhunen H(2013)Optimal placement of vertical connections in 3D Network-on-ChipJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.05.00259:7(441-454)Online publication date: 1-Aug-2013
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Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits

Shielding effect of on-chip interconnect inductance

Efficient Gate Delay Modeling for Large Interconnect Loads

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Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits

Shielding effect of on-chip interconnect inductance

Efficient Gate Delay Modeling for Large Interconnect Loads

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