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Compiler analysis and supports for leakage power reduction on microprocessors

Published: 25 July 2002 Publication History
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  • Abstract

    Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts also indicate architecture, compiler, and software participations can help reduce the switching activities (also known as dynamic power) on microprocessors. This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors. In this paper, we investigate the compiler analysis techniques related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating in the component levels. Our compiler gives an analysis framework to utilize the instruction to reduce the leakage power. We present a data flow analysis framework to estimate the component activities at fixed points of programs with the consideration of pipelines of architectures. We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions. As the duration of power gating on components on given program routines is related to program branches, we propose a set of scheduling policy include Basic_Blk_Sched, MIN_Path_Sched, and AVG_Path_Sched mechanisms and evaluate the effectiveness of those schemes. Our experiment is done by incorporating our compiler analysis and scheduling policy into SUIF compiler tools [32] and by simulating the energy consumptions on Wattch toolkits [6]. Experimental results show our mechanisms are effective in reducing leakage powers on microprocessors.

    References

    [1]
    Al Aburto, collections of common benchmarks of FAQ of comp. benchmarks USENET newsgroup, ftp site: ftp.nosc.mail/pub/aburto.
    [2]
    A. Aho, R. Sethi, J. Ullman, Compilers Principles, Techniques, and Tools, Addison-Wesley, 1985.
    [3]
    M. Alidina, J. Monteiro, S. Devadas, A. Ghosh and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power," Proc. of ICCAD-94, pp. 74-81, 1994.
    [4]
    Luca Benini and G. De Micheli, "State Assignment for Low Power Dissipation," IEEE Journal of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, March 1995.
    [5]
    Nikolaos Bellas, Ibrahim N. Hajj, and Constantine D. Polychronopoulos, "Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 317-326, June 2000.
    [6]
    D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a Framework for Architectural-Level Power Analysis and Optimizations," Proc. 27th. International Symposium on Computer Architecture, pp. 83-94, June 2000.
    [7]
    D. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0," Computer Architecture News, pp. 13-25, June 1997.
    [8]
    J. Adam Butts and Gurindar S. Sohi, "A Static Power Model for Architects," Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 191-201, December 2000.
    [9]
    R. G. Chang, T. R. Chuang, Jenq-Kuen Lee. "Efficient Support of Parallel Sparse Computation for Array Intrinsic Functions of Fortran 90," ACM International Conference on Supercomputing, Melbourne, Australia, July 13-17, 1998.
    [10]
    Rong-Guey Chang, Jia-Shing Li, Tyng-Ruey Chuang, Jenq Kuen Lee. "Probabilistic inference schemes for sparsity structures of Fortran 90 array intrinsics," International Conference on Parallel Processing, Spain, Sep. 2001.
    [11]
    A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, Vol. 27, No.4, pp. 473-484, April 1992.
    [12]
    Jui-Ming Chang, Massoud Pedram, "Register Allocation and Binding for Low Power," Proceedings of Design Automaton Conference, San Francisco, USA, June 1995.
    [13]
    Compaq Computer Corporation, Alpha 21264 Microprocessor Hardware Reference Manual, EC-RJRZA-TE, (July 1999).
    [14]
    V. De and S. Borkar, "Technology and design challenges for low power and high performance," Proc. of Int. Symp. Low Power Electronics and Design, pp. 163-168, 1999.
    [15]
    G. Hachtel, M. Hermida, A. Pardo, M. Poncino and F. Somenzi, "Re-Encoding Sequential Circuits to Reduce Power Dissipation," Proc. of ICCAD' 94, pp. 70-73, 1994.
    [16]
    G. Hadjiyiannis, S. Hanono and S. Devadas. "ISDL: An Instruction Set Description Language for Retargetability," Design Automation Conference, June 1997.
    [17]
    Yuan-Shin Hwang, Peng-Sheng Chen, Jenq-Kuen Lee, Roy Ju. "Probabilistic Points-to Analysis," LCPC '2001, Aug. 2001, USA.
    [18]
    Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju. "A Function-Composition Approach to Synthesize Fortran 90 Array Operations," Journal of Parallel and Distributed Computing, 54, 1-47, 1998.
    [19]
    Inki Hong, Darko Dirovski, et.al., "Power Optimization of Variable Voltage Core-Based Systems," Proc. of 35th DAC, pp. 176-181, 1998.
    [20]
    M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-Power Digital Design," Proceedings of the 1994 IEEE Symposium on Low Power Electronics, pp. 8-11.
    [21]
    Intel corporation, "Pentium III Processor for the SC242 at 450 MHz to 1.13 GHz Datasheet," pp. 26-30.
    [22]
    J. T. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for lowpower digital circuits," IEEE Journal of Solid-state circuits, 35(7):1009-1018, July 2000.
    [23]
    S. Kaxiras, Z. Hu and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," Proc. of the Int'l Symposium on Computer Architecture, pp.240-251, 2001.
    [24]
    Chingren Lee, Jenq Kuen Lee, TingTing Hwang, and Shi-Chun Tsai, "Compiler Optimization on Instruction Scheduling for Low Power," Proceedings of the 13th International Symposium on Systems Synthesis, pp. 55-60, September 2000.
    [25]
    Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita, "Power Analysis and Minimization Techniques for Embedded DSP Software," IEEE Transactions on VLSI Systems, Vol. 5, no. 1, pp. 123-133, March 1997.
    [26]
    M.D. Powell, S-H. Yang, B. Falsa, K. Roy, and T.N. Vijaykumar, "Gated-Vdd: a Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2000.
    [27]
    S. C. Prasad and K. Roy, "Circuit Activity Driven Multilevel Logic Optimization for Low Power Reliable Operation," Proceedings of the EDAC'93 EURO-ASIC, pp. 368-372, Feb., 1993.
    [28]
    S. Rele, S. Pande, S. Onder, and R. Gupta, "Optimizing Static Power Dissipation by Functional Units in Superscalar Processors," International Conference on Compiler Construction (CC), Grenoble, France, April 2002.
    [29]
    K. Roy and S. C. Prasad, "SYCLOP: Synthesis of CMOS Logic for Low Power Applications," Proceedings of the ICCD, pp. 464-467, 1992.
    [30]
    K. Roy, "Leakage Power reduction in Low-Voltage CMOS Designs," IEEE International Conference on Circuits and Systems, Vol. 2, pp. 167-173, 1998.
    [31]
    Michael D. Smith, "The SUIF Machine Library", Division of of Engineering and Applied Science, Harvard University, March 1998.
    [32]
    Stanford Compiler Group, "The SUIF Library", Stanford Compiler Group, Stanford, March 1995.
    [33]
    Ching-Long Su and Alvin M. Despain, "Cache Designs for Energy Efficiency," Proceedings of the 28th Annual Hawaii International Conference on System Sciences, pp. 306-315, 1995.
    [34]
    V. Tiwari, R. Donnelly, S. Malik, and R. Gonzalez, "Dynamic Power Management for Microprocessors: A Case Study," Proceedings of the 10th International Conference on VLSI Design, pp. 185-192, 1997.
    [35]
    V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, "Reducing Power in High-Performance Microprocessors," Proceedings of the Design Automaton Conference, pp. 732-737, 1998.
    [36]
    Scott Thompson, Paul Packan, and Mark Bohr, "MOS Scaling: Transistor Challenges for the 21st Century," Portland Technology Development, Intel Corp. Intel Technology Journal, Q3 1998.
    [37]
    C.Y. Tsui, M. Pedram, and A.M. Despain, "Technology Decomposition and Mapping Targeting Low Power Dissipation," Proc. of 30th Design Automaton Conf., pp.68-73, June 1993.
    [38]
    J. Z. Wu, Jenq-Kuen Lee. "A bytecode optimizer to engineer bytecodes for performances," LCPC 00, Aug. 2000, USA (Also in LNCS 2017).
    [39]
    Yi-Ping You, Ching-Ren Lee, Jenq-Kuen Lee, Wei-Kuan Shih. "Rea-Time Task Scheduling for Dynamically Variable Voltage Processors," IEEE workshop on Power Management for Real-Time and Embedded Systems, May 2001.
    [40]
    W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte, and Y. Tsai. "Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction," Proceedings of the Thirty-Fourth Annual International Symposium on Microarchitecture (MICRO-34). pp. 102-113. Austin, TX. December 2001.

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    • (2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
    • (2014)Compiler Optimization for Reducing Leakage Power in Multithread BSP ProgramsACM Transactions on Design Automation of Electronic Systems10.1145/266811920:1(1-34)Online publication date: 18-Nov-2014
    • (2013)Energy-aware code motion for GPU shader processorsACM Transactions on Embedded Computing Systems10.1145/2539036.253904513:3(1-24)Online publication date: 24-Dec-2013
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        Published In

        cover image Guide Proceedings
        LCPC'02: Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
        July 2002
        376 pages
        ISBN:3540307818
        • Editors:
        • Bill Pugh,
        • Chau-Wen Tseng

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        • UMIACS: U of MD Inst for Advanced Comp Studies

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        Springer-Verlag

        Berlin, Heidelberg

        Publication History

        Published: 25 July 2002

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        • (2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
        • (2014)Compiler Optimization for Reducing Leakage Power in Multithread BSP ProgramsACM Transactions on Design Automation of Electronic Systems10.1145/266811920:1(1-34)Online publication date: 18-Nov-2014
        • (2013)Energy-aware code motion for GPU shader processorsACM Transactions on Embedded Computing Systems10.1145/2539036.253904513:3(1-24)Online publication date: 24-Dec-2013
        • (2013)Power devilProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443615(29-34)Online publication date: 24-Feb-2013
        • (2007)Compilation for compact power-gating controlsACM Transactions on Design Automation of Electronic Systems10.1145/1278349.127836412:4(51-es)Online publication date: 1-Sep-2007
        • (2005)A sink-n-hoist framework for leakage power reductionProceedings of the 5th ACM international conference on Embedded software10.1145/1086228.1086252(124-133)Online publication date: 18-Sep-2005
        • (2004)Power-Aware scheduling for parallel security processors with analytical modelsProceedings of the 17th international conference on Languages and Compilers for High Performance Computing10.1007/11532378_33(470-484)Online publication date: 22-Sep-2004
        • (2003)Compiler support for speculative multithreading architecture with probabilistic points-to analysisACM SIGPLAN Notices10.1145/966049.78150238:10(25-36)Online publication date: 11-Jun-2003
        • (2003)Compiler support for speculative multithreading architecture with probabilistic points-to analysisProceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming10.1145/781498.781502(25-36)Online publication date: 11-Jun-2003

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