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Semi-modularity and testability of speed-independent circuits

Authors:

Peter A. Beerel,

Teresa H.-Y. MengAuthors Info & Claims

Integration, the VLSI Journal, Volume 13, Issue 3

Pages 301 - 322

https://doi.org/10.1016/0167-9260(92)90033-U

Published: 01 September 1992 Publication History

Abstract

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Cited By

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Efthymiou A(2010)Initialization-based test pattern generation for asynchronous circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201347018:4(591-601)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013470
Ruan JWang ZDai KLi Y(2007)Design and test of self-checking asynchronous control circuitProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391834(320-329)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.5555/2391795.2391834
Efthymiou ABainbridge JEdwards D(2005)Test pattern generation and partial-scan methodology for an asynchronous SoC interconnectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86272213:12(1384-1393)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.862722
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Index Terms

Semi-modularity and testability of speed-independent circuits
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Hardware test
    1. Design for testability

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Published In

cover image Integration, the VLSI Journal

Integration, the VLSI Journal Volume 13, Issue 3

Special issue on high-level synthesis

Sept. 1992

112 pages

ISSN:0167-9260

Editor:
R. H. J. M. Otten
Delft Univ. of Technology, Delft, The Netherlands

Issue’s Table of Contents

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 September 1992

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Efthymiou A(2010)Initialization-based test pattern generation for asynchronous circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201347018:4(591-601)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013470
Ruan JWang ZDai KLi Y(2007)Design and test of self-checking asynchronous control circuitProceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation10.5555/2391795.2391834(320-329)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.5555/2391795.2391834
Efthymiou ABainbridge JEdwards D(2005)Test pattern generation and partial-scan methodology for an asynchronous SoC interconnectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86272213:12(1384-1393)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.862722
Liebelt MBurgess N(1999)Detecting Exitory Stuck-At Faults in Semimodular Asynchronous CircuitsIEEE Transactions on Computers10.1109/12.76253848:4(442-448)Online publication date: 1-Apr-1999
https://dl.acm.org/doi/10.1109/12.762538
Saposhnikov VMoshanin VSaposhnikov VGoessel M(1999)Experimental Results for Self-Dual Multi-Output Combinational CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100837040560714:3(295-300)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1023/A%3A1008370405607
Beerel PBurch JMeng T(1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1023/A%3A1008666605437
Roig OCortadella JPeña MPastor EYoffa EDe Micheli GRabaey J(1997)Automatic generation of synchronous test patterns for asynchronous circuitsProceedings of the 34th annual Design Automation Conference10.1145/266021.266300(620-625)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266300
Lin KKuo CLin C(1997)Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic GraphIEEE Transactions on Computers10.1109/12.64429946:11(1246-1263)Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.1109/12.644299
Banerjee SChakradhar sRoy R(1996)Synchronous Test Generation Model for Asynchronous CircuitsProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834779Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834779
Piestrak SNanya T(1995)Towards Totally Self-Checking Delay-Insensitive SystemsProceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing10.5555/874064.875618Online publication date: 27-Jun-1995
https://dl.acm.org/doi/10.5555/874064.875618
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Recommendations

Delay Fault Testability on Two-Rail Logic Circuits

Decomposition and technology mapping of speed-independent circuits using Boolean relations

Checking Combinational Equivalence of Speed-Independent Circuits

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