article

Interconnect intellectual property for network-on-chip (NoC)

Authors:

Hannu TenhunenAuthors Info & Claims

Journal of Systems Architecture: the EUROMICRO Journal, Volume 50, Issue 2-3

Pages 65 - 79

https://doi.org/10.1016/j.sysarc.2003.07.003

Published: 01 February 2004 Publication History

Abstract

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network on chip: an architecture for billion transistor era, in: Proceeding of the IEEE NorChip Conference, November 2000; Network on chip, in: Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm, June 2002]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. Within an IIP, the switch has the central function. Depending on the network core of the NoC, the switch will have different architectures and implementations. This paper first briefly introduces the concept of NoC. It then studies NoC from an interconnect point of view and makes projections on future NoC parameters. At last, the IIP and its components are described, the switch is studied in more detail and a time-space-time (TST) switch designed for a circuit switched time-division multiplexing (TDM) NoC is proposed. This switch supports multicast traffic and is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.

References

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Cited By

Samman FHollstein TGlesner M(2018)Adaptive and deadlock-free tree-based multicast routing for networks-on-chipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201975818:7(1067-1080)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2019758
Stefan RGoossens KFlich JBertozzi DSkeie TLudovici D(2011)An improved algorithm for slot selection in the Æthereal network-on-chipProceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip10.1145/1930037.1930040(7-10)Online publication date: 23-Jan-2011
https://dl.acm.org/doi/10.1145/1930037.1930040
Jerger NPeh LLipasti M(2008)Virtual Circuit Tree MulticastingACM SIGARCH Computer Architecture News10.1145/1394608.138214136:3(229-240)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382141
Show More Cited By

Index Terms

Interconnect intellectual property for network-on-chip (NoC)
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors
2. Networks
  1. Network protocols
  2. Network types
    1. Wired access networks

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Published In

cover image Journal of Systems Architecture: the EUROMICRO Journal

Journal of Systems Architecture: the EUROMICRO Journal Volume 50, Issue 2-3

Special issue: Networks on chip

February 2004

101 pages

ISSN:1383-7621

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Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 February 2004

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Cited By

Samman FHollstein TGlesner M(2018)Adaptive and deadlock-free tree-based multicast routing for networks-on-chipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201975818:7(1067-1080)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2019758
Stefan RGoossens KFlich JBertozzi DSkeie TLudovici D(2011)An improved algorithm for slot selection in the Æthereal network-on-chipProceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip10.1145/1930037.1930040(7-10)Online publication date: 23-Jan-2011
https://dl.acm.org/doi/10.1145/1930037.1930040
Jerger NPeh LLipasti M(2008)Virtual Circuit Tree MulticastingACM SIGARCH Computer Architecture News10.1145/1394608.138214136:3(229-240)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382141
Rodrigo SFlich JDuato JHummel M(2008)Efficient unicast and multicast support for CMPsProceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2008.4771805(364-375)Online publication date: 8-Nov-2008
https://dl.acm.org/doi/10.1109/MICRO.2008.4771805
Jerger NPeh LLipasti M(2008)Virtual Circuit Tree MulticastingProceedings of the 35th Annual International Symposium on Computer Architecture10.1109/ISCA.2008.12(229-240)Online publication date: 21-Jun-2008
https://dl.acm.org/doi/10.1109/ISCA.2008.12
Bolotin ECidon IGinosar RKolodny ALauwereins RMadsen J(2007)Routing table minimization for irregular mesh NoCsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266570(942-947)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266570
Bjerregaard TMahadevan S(2006)A survey of research and practices of Network-on-chipACM Computing Surveys (CSUR)10.1145/1132952.113295338:1(1-es)Online publication date: 29-Jun-2006
https://dl.acm.org/doi/10.1145/1132952.1132953
Weerasekera RZheng LPamunuwa DTenhunen H(2005)Switching sensitive driver circuit to combat dynamic delay in on-chip busesProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_29(277-285)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_29

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