article

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

Authors:

S. Bernard,

F. Azaïs,

Y. Bertrand,

M. RenovellAuthors Info & Claims

Journal of Electronic Testing: Theory and Applications, Volume 19, Issue 4

Pages 469 - 479

https://doi.org/10.1023/A:1024652328578

Published: 01 August 2003 Publication History

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Abstract

In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal. In a second step, a very high accuracy triangle-wave signal generator is presented in order to improve the equivalent linearity of the generated analog test signal.

References

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Korhonen EKostamovaara J(2019)On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairsAnalog Integrated Circuits and Signal Processing10.1007/s10470-010-9496-267:1(21-29)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-010-9496-2

Index Terms

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
1. General and reference
  1. Cross-computing tools and techniques
    1. Measurement
2. Hardware

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cover image Journal of Electronic Testing: Theory and Applications

Journal of Electronic Testing: Theory and Applications Volume 19, Issue 4

August 2003

121 pages

ISSN:0923-8174

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Kluwer Academic Publishers

United States

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Published: 01 August 2003

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Korhonen EKostamovaara J(2019)On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairsAnalog Integrated Circuits and Signal Processing10.1007/s10470-010-9496-267:1(21-29)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s10470-010-9496-2

Abstract

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Cited By

Index Terms

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A novel time-interleaved two-step single-slope ADC architecture based on both resistor ladder and current source ramp generator

A 10-bit 50MS/s SAR ADC in 65nm CMOS with on-chip reference voltage buffer

A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

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