research-article

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting

Authors:

M. PoncinoAuthors Info & Claims

IEEE Transactions on Computers, Volume 48, Issue 8

Pages 769 - 779

https://doi.org/10.1109/12.795120

Published: 01 August 1999 Publication History

Abstract

In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.

References

[1]

S.F. Oberman and M.J. Flynn, “Design Issues in Division and Other Floating-Point Operations,” IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997.

Digital Library

[2]

L. Benini G. De Micheli E. Macii and M. Poncino, “Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220-232, Mar. 1998.

Digital Library

[3]

R.I. Bahar E.A. Frohm C.M. Gaona G.D. Hachtel E. Macii A. Pardo and F. Somenzi, “Algebraic Decision Diagrams and Their Applications,” Formal Methods in System Design, vol. 10, pp. 171-206, 1997.

Digital Library

[4]

R.I. Bahar H. Cho G.D. Hachtel E. Macii F. Somenzi, “Symbolic Timing Analysis and Re-Synthesis for Low Power of Combinational Circuits Containing False Paths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, pp. 1,101-1,115 Oct. 1997.

Digital Library

[5]

P.C. McGeer and R.K. Brayton, Integrating Functional and Temporal Domains in Logic Synthesis. Boston, Mass.: Kluwer Academic, 1991.

Digital Library

[6]

F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” Proc. ISCAS-85: IEEE Int'l Symp. Circuits and Systems, pp. 785-794, Kyoto, Japan, June 1985.

[7]

F. Brglez D. Bryan and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Proc. ISCAS-89: IEEE Int'l Symp. Circuits and Systems, pp. 1,929-1,934, Portland, Ore., May 1989.

[8]

T.H. Cormen C.E. Leiserson and R.L. Rivest, An Introduction to Algorithms. New York: McGraw-Hill, 1990.

Digital Library

[9]

R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. 35, no. 8, pp. 79-85, Aug. 1986.

Digital Library

[10]

R. Bryant, “Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams,” ACM Computing Surveys, vol. 24, no. 3, pp. 293-318, Sept. 1992.

Digital Library

[11]

D. Brand and V.S. Iyengar, “Timing Analysis Using Functional Analysis,” Proc. ICCAD-86: Int'l Conf. Computer-Aided Design, pp. 126-129, Santa Clara, Calif., Nov. 1986.

[12]

H.C. Chen and D.H.C. Du, “Path Sensitization in Critical Paths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 196-207, Feb. 1993

Digital Library

[13]

S. Devadas K. Keutzer and S. Malik, “Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1,913-1,923, Dec. 1993.

[14]

E.M. Sentovich K.J. Singh C.W. Moon H. Savoj R.K. Brayton A. Sangiovanni-Vincentelli, “Sequential Circuits Design Using Synthesis and Optimization,” Proc. ICCD-92: IEEE Int'l Conf. Computer Design, pp. 328-333, Cambridge, Mass., Oct. 1992.

Digital Library

[15]

F. Somenzi, CUDD: University of Colorado Decision Diagram Package, Release 2.1.2, technical report, Dept. of Electrical and Computer Eng., Univ. of Colorado, Boulder, Apr. 1997.

[16]

R.E. Bryant, “On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication,” IEEE Trans. Computers, vol. 40, no. 2, pp. 205-213, Feb. 1991.

Digital Library

Cited By

Tsai CCheng CHuang NWu K(2017)Analysis and optimization of variable-latency designs in the presence of timing variabilityProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130665(1219-1224)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130665
De VKahng AKarnik TLiu BMaleki MWang L(2015)Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignACM Journal on Emerging Technologies in Computing Systems10.1145/274634112:3(1-19)Online publication date: 21-Sep-2015
https://dl.acm.org/doi/10.1145/2746341
Hyman RRanganathan NBingel TVo D(2013)A clock control strategy for peak power and RMS current reduction using path clusteringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218698921:2(259-269)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2186989
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Index Terms

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 48, Issue 8

August 1999

97 pages

ISSN:0018-9340

Editor:
Jean-Luc Gaudiot
Univ. of Southern California, Los Angeles

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Copyright © Copyright © 1999 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 August 1999

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Cited By

Tsai CCheng CHuang NWu K(2017)Analysis and optimization of variable-latency designs in the presence of timing variabilityProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130665(1219-1224)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130665
De VKahng AKarnik TLiu BMaleki MWang L(2015)Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignACM Journal on Emerging Technologies in Computing Systems10.1145/274634112:3(1-19)Online publication date: 21-Sep-2015
https://dl.acm.org/doi/10.1145/2746341
Hyman RRanganathan NBingel TVo D(2013)A clock control strategy for peak power and RMS current reduction using path clusteringIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218698921:2(259-269)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2186989
Galceran-Oms MGotmanov ACortadella JKishinevsky M(2011)Microarchitectural Transformations Using ElasticityACM Journal on Emerging Technologies in Computing Systems10.1145/2043643.20436487:4(1-24)Online publication date: 1-Dec-2011
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(2010)Elastic systemsProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558639(149-158)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558639
Banñeres DCortadella JKishinevsky MBenini LDe Micheli GAl-Hashimi BMueller W(2009)Variable-latency design by function speculationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875026(1704-1709)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875026
Choudhury MMohanram KBenini LDe Micheli GAl-Hashimi BMueller W(2009)Masking timing errors on speed-paths in logic circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874642(87-92)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874642
Choudhury MMohanram K(2009)Timing-driven optimization using lookahead logic circuitsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630015(390-395)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630015
Galceran-Oms MCortadella JKishinevsky M(2009)Speculation in elastic systemsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629989(292-295)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629989
Carmona JCortadella JKishinevsky MTaubin A(2009)Elastic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203043628:10(1437-1455)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030436
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