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A Fault-Tolerant Digital Artificial Neuron

Published: 01 October 1993 Publication History

Abstract

A simple fault-tolerant digital artificial neuron is introduced. Two digital implementations based on two different adders are examined. Reliability, fault coverage, and hardware redundancy analyses are carried out to characterize the proposed fault-tolerant digital neural module. These analyses reveal that, for a 114% increase in hardware, a 92.07% fault detection coverage and a 21.15% fault recovery coverage are attained for a four-input neural module.

References

[1]
1. T. Sejnowski, "Neural Network Learning Algorithms," Neural Computers , R. Eckmiller and C. Malsburg, eds., Springer-Verlag, Berlin, 1989, pp. 291-300.
[2]
2. K. Knight, "Connectionist Ideas and Algorithms," Comm. ACM, Vol. 33, No. 11, New York, Nov. 1990, pp. 59-74.
[3]
3. R. Hecht-Nielsen, Neurocomputing, Addison-Wesley, Reading, Mass., 1990.
[4]
1. W. Moore, "Conventional Fault Tolerance and Neural Computers," Neural Computers , R. Eckmiller and C. Malsburg, eds., Springer-Verlag, Berlin, 1989, pp. 29-37.
[5]
2. L. Belfore, B.W. Johnson, and J.H. Aylor, "The Design of Inherently Fault-Tolerant Systems," Concurrent Computations, S.K. Tewksbury et al., eds., Plenum Press, N.Y., 1988, pp. 565-583.
[6]
3. Q. Xu et al., "A Fault Tolerance Analysis of a Neocognitron Model," Proc. Int'l Joint Conf. Neural Networks, Vol. II, Washington, D.C., Jan. 1990, pp. II559-II562.
[7]
4. P. Franzon et al., "Defect Tolerant Implementations of Feed-Forward and Recurrent Neural Networks," Proc. IEEE Int'l Conf. Wafer Scale Integration, IEEE Computer Society Press, Los Alamitos, Calif, 1990, pp. 160-166.
[8]
5. M. Stevenson, R. Winter, and B. Widrow, "Sensitivity of Layered Neural Networks to Errors in the Weights," Proc. Int'l Joint Conf. Neural Networks, Vol. 1, Washington, D.C., Jan. 1990, pp. I337-I340.
[9]
1. J. Nijhuis et al., "Limits to the Fault Tolerance of a Feedforward Neural Network with Learning," Proc. 20th Int'l Symp. Fault-Tolerant Computing, New-Castle-Upon-Tyne, UK, June 1990, pp. 228-235.
[10]
2. L. Belfore, B.W. Johnson, and J.H. Aylor, "The Design of Inherently Fault-Tolerant Systems," in Concurrent Computations, S.K. Tewksbury et al., eds., Plenum Press, N.Y., 1988, pp. 565-583.
[11]
3. U. Ramacher and J. Beichter, "Architecture of a Systolic Neuro-Emulator," Proc. Int'l Joint Conf. Neural Networks, Vol. II, Washington, D.C., Jan. 1990, pp. II59- II63.
[12]
4. Y. Tohma, "Coding Techniques in Fault-Tolerant Self-Checking, and Fail-Safe Circuits," in Fault-Tolerant Computing, D.K. Pradhan, ed., Prentice Hall, Englewood Cliffs, NJ, 1986, pp. 336-411.
[13]
5. K. Hwang, Computer Arithmetic, J. Wiley & Sons, New York, 1979.
[14]
6. B.W. Johnson, Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, Reading, Mass., 1989.

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cover image IEEE Design & Test
IEEE Design & Test  Volume 10, Issue 4
October 1993
86 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 October 1993

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