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Introduction to High-Level Synthesis

Authors:

Daniel D. Gajski,

Loganath RamachandranAuthors Info & Claims

IEEE Design & Test, Volume 11, Issue 4

Pages 44 - 54

https://doi.org/10.1109/54.329454

Published: 01 October 1994 Publication History

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Abstract

The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology.

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Cited By

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Shi SPundir NKamali HTehranipoor MFarahmandi FTakahashi A(2023)SecHLSProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567926(585-590)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567926
Pundir NAftabjahani SCammarota RTehranipoor MFarahmandi F(2022)Analyzing Security Vulnerabilities Induced by High-level SynthesisACM Journal on Emerging Technologies in Computing Systems10.1145/349234518:3(1-22)Online publication date: 29-Jan-2022
https://dl.acm.org/doi/10.1145/3492345
Abderehman MGupta RTheegala RKarfa C(2022)BLAST: Belling the Black-Hat High-Level Synthesis ToolIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320051341:11(3661-3672)Online publication date: 1-Nov-2022
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Index Terms

Introduction to High-Level Synthesis
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Robustness

Index terms have been assigned to the content through auto-classification.

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Published In

IEEE Design & Test Volume 11, Issue 4

October 1994

81 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 October 1994

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Shi SPundir NKamali HTehranipoor MFarahmandi FTakahashi A(2023)SecHLSProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567926(585-590)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567926
Pundir NAftabjahani SCammarota RTehranipoor MFarahmandi F(2022)Analyzing Security Vulnerabilities Induced by High-level SynthesisACM Journal on Emerging Technologies in Computing Systems10.1145/349234518:3(1-22)Online publication date: 29-Jan-2022
https://dl.acm.org/doi/10.1145/3492345
Abderehman MGupta RTheegala RKarfa C(2022)BLAST: Belling the Black-Hat High-Level Synthesis ToolIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320051341:11(3661-3672)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3200513
Gao XWickerson JConstantinides GChen DGreene J(2016)Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level SynthesisProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847282(234-243)Online publication date: 21-Feb-2016
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Lattuada MFerrandi FMarculescu DLiu F(2015)Code Transformations Based on Speculative SDC SchedulingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840830(71-77)Online publication date: 2-Nov-2015
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Horváth PHosszú GKovács F(2015)A proposed synthesis method for Application-Specific Instruction Set ProcessorsMicroelectronics Journal10.1016/j.mejo.2015.01.00146:3(237-247)Online publication date: 1-Mar-2015
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Kavvadias NMasselos KKetikidis PMargaritis KVlahavas IChatzigeorgiou AEleftherakis GStamelos I(2013)Hardware design space exploration using HercuLeS HLSProceedings of the 17th Panhellenic Conference on Informatics10.1145/2491845.2491865(195-202)Online publication date: 19-Sep-2013
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Alizadeh BFujita MLin Y(2010)Guided gate-level ATPG for sequential circuits using a high-level test generation approachProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899824(425-430)Online publication date: 18-Jan-2010
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Alizadeh BMirzaei MFujita M(2010)Coverage driven high-level test generation using a polynomial model of sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204357129:5(737-748)Online publication date: 1-May-2010
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Kim YMansouri NNarayanan VYan ZMacii EBhanja S(2008)Automated formal verification of scheduling with speculative code motionsProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366134(95-100)Online publication date: 4-May-2008
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Cited By

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Recommendations

An Introduction to High-Level Synthesis

High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective

Layout-driven RTL binding techniques for high-level synthesis

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