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Partial bus-invert coding for power optimization of application-specific systems

Published: 01 April 2001 Publication History

Abstract

This paper presents two bus coding schemes for power optimization of application-specific systems: partial pus-invert coding and its extension to multiway partial bus-invert coding. In the first scheme, only a selected subgroup of bus lines is encoded to avoid unnecessary inversion of relatively inactive and/or uncorrelated bus lines which are not included in the subgroup. In the extended scheme, we partition a bus into multiple subbuses by clustering highly correlated bus lines and then encode each subbus independently. We describe a heuristic algorithm of partitioning a bus into subbuses for each encoding scheme. Experimental results for various examples indicate that both encoding schemes are highly efficient for application-specific systems.

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Farnaz Toussi

This paper extends the conventional bus-invert (BI) coding to reduce the number of bus transitions, and thus, the dynamic power consumption. The proposed coding, partial bus-invert (PBI), simply divides the bus into two or more subbuses, and based on the last transition pattern and the current transition pattern, determines whether or not to invert a subbus. In particular, if less than half of the bus lines within a subbus cause a transition, the subbus is inverted and the invert line of the subbus is set. The experimental results indicate significant reduction in bus switching. However, one of the limitations of this scheme is that the access patterns must be known ahead of time in order to divide the bus into subbuses and add additional invert lines (one per subbus). Although more subbuses show significant improvement, the additional invert lines, I/O pins and I/O drivers limit the number of subbuses that can be implemented. Nevertheless, in addition to reducing power, the proposed scheme can potentially reduce the impact of crosstalk noise. Overall, the paper’s presentation is good, but the experimental results and their comparisons with previous work are not described well. In particular, in each experiment, the PBI is compared with a different scheme and the authors do not explain why this is the case. Online Computing Reviews Service

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 9, Issue 2
April 2001
177 pages
ISSN:1063-8210
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IEEE Educational Activities Department

United States

Publication History

Published: 01 April 2001

Author Tags

  1. digital complementary metal—oxide—semiconductor
  2. trade-off

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  • (2011)GPHMicroprocessors & Microsystems10.1016/j.micpro.2010.09.00535:1(68-80)Online publication date: 1-Feb-2011
  • (2009)An efficient segmental bus-invert coding method for instruction memory data bus switching reductionEURASIP Journal on Embedded Systems10.1155/2009/9739762009(1-10)Online publication date: 1-Jan-2009
  • (2008)DS2ISJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2007.08.00254:1-2(324-334)Online publication date: 1-Jan-2008
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  • (2007)Timing-driven row-based power gatingProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283803(104-109)Online publication date: 27-Aug-2007
  • (2007)Power optimal MTCMOS repeater insertion for global busesProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283802(98-103)Online publication date: 27-Aug-2007
  • (2006)Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designsProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123030(114-119)Online publication date: 9-Apr-2006
  • (2006)Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.87437314:4(421-425)Online publication date: 1-Apr-2006
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