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10.1109/ISPASS.2005.1430560guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Accelerating Multiprocessor Simulation with a Memory Timestamp Record

Published: 20 March 2005 Publication History
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    • (2020)PAQSIMThe 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3372799.3394359(3-14)Online publication date: 16-Jun-2020
    • (2019)Directed Statistical Warming through Time TravelingProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358264(1037-1049)Online publication date: 12-Oct-2019
    • (2017)Efficient Generation of Compact Execution Traces for Multicore Architectural SimulationsACM Transactions on Architecture and Code Optimization10.1145/310634214:3(1-25)Online publication date: 30-Aug-2017
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        cover image Guide Proceedings
        ISPASS '05: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
        March 2005
        286 pages
        ISBN:0780389654

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        IEEE Computer Society

        United States

        Publication History

        Published: 20 March 2005

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        • (2020)PAQSIMThe 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3372799.3394359(3-14)Online publication date: 16-Jun-2020
        • (2019)Directed Statistical Warming through Time TravelingProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358264(1037-1049)Online publication date: 12-Oct-2019
        • (2017)Efficient Generation of Compact Execution Traces for Multicore Architectural SimulationsACM Transactions on Architecture and Code Optimization10.1145/310634214:3(1-25)Online publication date: 30-Aug-2017
        • (2011)SniperProceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/2063384.2063454(1-12)Online publication date: 12-Nov-2011
        • (2010)Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approachSoftware—Practice & Experience10.5555/1751626.175162940:3(239-258)Online publication date: 1-Mar-2010
        • (2009)Branch Predictor Warmup for Sampled Simulation through Branch History MatchingTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_4(45-64)Online publication date: 22-Apr-2009
        • (2007)Branch history matchingProceedings of the 2nd international conference on High performance embedded architectures and compilers10.5555/1762146.1762162(153-167)Online publication date: 28-Jan-2007
        • (2006)Simulation of Computer ArchitecturesIEEE Transactions on Computers10.1109/TC.2006.4455:3(268-280)Online publication date: 1-Mar-2006
        • (2006)NSL-BLRLProceedings of the 39th annual Symposium on Simulation10.1109/ANSS.2006.33(168-177)Online publication date: 2-Apr-2006
        • (2005)Victim ReplicationACM SIGARCH Computer Architecture News10.1145/1080695.106999833:2(336-345)Online publication date: 1-May-2005
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