Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
research-article

The Future of Simulation: A Field of Dreams

Published: 01 November 2006 Publication History
  • Get Citation Alerts
  • Abstract

    Improving the infrastructure, benchmarking, and methodology of simulation--the dominant computer performance evaluation method--will result in higher efficiency and let architects gain more insight into processor behavior.

    References

    [1]
    K. Skadron et al., "Challenges in Computer Architecture Evaluation," Computer, Aug. 2003, pp. 30–36.
    [2]
    M. Vachharajani et al., "Microarchitectural Exploration with Liberty," Proc. 35th Ann. Int'l Symp. Microarchitecture, IEEE CS Press, 2002, pp. 271–282.
    [3]
    T. Karkhanis and J. Smith, "Modeling Superscalar Processors," Proc. 31st Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2004, pp. 338–349.
    [4]
    T. Sherwood, M. Oskin, and B. Calder, "Balancing Design Options with Sherpa," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems, ACM Press, 2004, pp. 57–68.
    [5]
    S. Nussbaum and J. Smith, "Modeling Superscalar Processors via Statistical Simulation," Proc. 11th Ann. Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2001, pp. 15–24.
    [6]
    L. Eeckhout et al., "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies," Proc. 31st Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2004, pp. 351–362.
    [7]
    S. Narayanasamy et al., "Automatic Logging of Operating System Effects to Guide Application-Level Architecture Simulation," Proc. Joint Int'l Conf. Measurement and Modeling of Computer Systems, ACM Press, 2006, pp. 216–227.
    [8]
    T. Sherwood et al., "Automatically Characterizing Large Scale Program Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 2002, pp. 45–57.
    [9]
    R. Wunderlich et al., "SMARTS: Accelerating Microarchitectural Simulation via Rigorous Statistical Sampling," Proc. 30th Ann. Int'l Symp. Computer Architecture, ACM Press, 2003, pp. 84–95.
    [10]
    S. Girbal et al., "DiST: A Simple, Reliable and Scalable Method to Significantly Reduce Processor Architecture Simulation Time," Proc. 2003 ACM Sigmetrics Int'l Conf. Measurement and Modeling of Computer Systems, ACM Press, 2003, pp. 1–12.
    [11]
    M. Van Biesbrouck, L. Eeckhout, and B. Calder, "Efficient Sampling Startup for Sampled Processor Simulation," Proc. 2005 Int'l Conf. High Performance Embedded Architectures and Compilers, Springer, 2005, pp. 47–67.
    [12]
    J. Haskins Jr. and K. Skadron, "Memory Reference Reuse Latency: Accelerated Warmup for Sampled Microarchitecture Simulation," Proc. 2003 Int'l Symp. Performance Analysis of Systems and Software, IEEE Press, 2003, pp. 195–203.
    [13]
    J. Yi et al., "Characterizing and Comparing Prevailing Simulation Methodologies," Proc. 11th Ann. Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 2005, pp. 266–277.
    [14]
    J. Yi, D. Lilja, and D. Hawkins, "A Statistically Rigorous Approach for Improving Simulation Methodology," Proc. 9th Ann. Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 2003, pp. 281–291.
    [15]
    L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Workload Design: Selecting Representative Program-Input Pairs," Proc. 11th Ann. Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2002, pp. 83–94.
    [16]
    M. Oskin, F. Chong, and M. Farrens, "HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Design," Proc. 27th Ann. Int'l Symp. Computer Architecture, ACM Press, 2000, pp. 71–82.
    [17]
    S. Nussbaum and J. Smith, "Modeling Superscalar Processors via Statistical Simulation," Proc. 10th Ann. Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2001, pp. 15–24.
    [18]
    L. Eeckhout et al., "Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox," IEEE Micro, Sept./Oct. 2003, pp.26–38.
    [19]
    L. Eeckhout et al., "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies," Proc. 31st Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2004, pp. 350–361.
    [20]
    D. Genbrugge, L. Eeckhout, and K. De Bosschere, "Accurate Memory Data Flow Modeling in Statistical Simulation," Proc. 20th Ann. Int'l Conf. Supercomputing, IEEE CS Press, 2006.
    [21]
    S. Eyerman, L. Eeckhout, and K. De Bosschere, "Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors," Proc. Conf. Design Automation and Test in Europe, European Design and Automation Association, 2006, pp. 351–356.
    [22]
    A. Joshi et al., "Evaluating the Efficacy of Statistical Simulation for Design Space Exploration," Proc. IEEE Symp. Performance Analysis of Systems and Software, IEEE Press, 2006, pp. 70–79.
    [23]
    S. Laha, J. Patel, and R. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. Computers, Nov. 1988, pp. 1325–1336.
    [24]
    T. Conte, "Systematic Computer Architecture Prototyping," doctoral dissertation, Dept. Electrical and Computer Eng., Univ. of Illinois at Urbana-Champaign, 1992.
    [25]
    T. Conte, M. Hirsch, and W. Hwu, "Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation," IEEE Trans. Computers, June 1998, pp. 714–720.
    [26]
    M. Van Biesbrouck, L. Eeckhout, and B. Calder, "Efficient Sampling Startup for Sampled Processor Simulation," Proc. Int'l Conf. High Performance Embedded Architectures and Compilers, Springer, 2005, pp. 47–67.
    [27]
    R. Wunderlich et al., "SMARTS: Accelerating Microarchitectural Simulation via Rigorous Statistical Sampling," Proc. 30th Ann. Int'l Symp. Computer Architecture, ACM Press, 2003, pp. 84–95.
    [28]
    T. Sherwood et al., "Automatically Characterizing Large Scale Program Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 2002, pp. 45–57.

    Cited By

    View all
    • (2018)Fast parallel simulation of a manycore architecture with a flit-level on-chip network modelProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229647(115-122)Online publication date: 15-Jul-2018
    • (2016)TQSIMJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.04.01266:C(33-47)Online publication date: 1-May-2016
    • (2015)Automated design space exploration with AspenScientific Programming10.1155/2015/1573052015(7-7)Online publication date: 1-Jan-2015
    • Show More Cited By

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image Computer
    Computer  Volume 39, Issue 11
    November 2006
    99 pages

    Publisher

    IEEE Computer Society Press

    Washington, DC, United States

    Publication History

    Published: 01 November 2006

    Author Tags

    1. Computer performance evaluation
    2. Processor performance
    3. Simulation

    Qualifiers

    • Research-article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 12 Aug 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2018)Fast parallel simulation of a manycore architecture with a flit-level on-chip network modelProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229647(115-122)Online publication date: 15-Jul-2018
    • (2016)TQSIMJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.04.01266:C(33-47)Online publication date: 1-May-2016
    • (2015)Automated design space exploration with AspenScientific Programming10.1155/2015/1573052015(7-7)Online publication date: 1-Jan-2015
    • (2015)Two-Level Hybrid Sampled Simulation of Multithreaded ApplicationsACM Transactions on Architecture and Code Optimization10.1145/281835312:4(1-25)Online publication date: 16-Nov-2015
    • (2015)Robust Design Space ModelingACM Transactions on Design Automation of Electronic Systems10.1145/266811820:2(1-22)Online publication date: 2-Mar-2015
    • (2013)Accurately modeling superscalar processor performance with reduced traceJournal of Parallel and Distributed Computing10.1016/j.jpdc.2012.12.00273:4(509-521)Online publication date: 1-Apr-2013
    • (2012)On the simulation of large-scale architectures using multiple application abstraction levelsACM Transactions on Architecture and Code Optimization10.1145/2086696.20867158:4(1-20)Online publication date: 26-Jan-2012
    • (2011)Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRsACM Transactions on Architecture and Code Optimization10.1145/2019608.20196098:3(1-28)Online publication date: 18-Oct-2011
    • (2010)Automated modeling and emulation of interconnect designs for many-core chip multiprocessorsProceedings of the 47th Design Automation Conference10.1145/1837274.1837383(431-436)Online publication date: 13-Jun-2010
    • (2010)P-GASProceedings of the 2010 IEEE Workshop on Principles of Advanced and Distributed Simulation10.1109/PADS.2010.5471655(89-96)Online publication date: 17-May-2010
    • Show More Cited By

    View Options

    View options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media