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Toward high performance nonblocking software transactional memory

Published: 20 February 2008 Publication History
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  • Abstract

    Substantial advances in STM performance in recent years have mostly focused on blocking systems. We describe our work integrating the most important techniques and optimizations emerging from the recent work on blocking STMs into several variants of a nonblocking STM.
    In particular, our design is based on the philosophy of keeping the common, contention free execution path as simple (consequently fast) as possible, while resorting to the more expensive data displacement and metadata management only in situations where transactions have problems making forward progress. We employ novel ownership "stealing" and metadata management techniques in our nonblocking STM to enable several recent blocking STM optimizations such as timestamp-based validation and ownership release via store instructions, all leading to a more streamlined and efficient fast path. We present an undo log (eager versioning) variant of our STM, as well as two redo log (lazy versioning) variants, the latter of which are based on the two ownership acquisition techniques (namely eager and lazy) for writes made by transactions.
    Experimental results show that our efforts have improved the performance of nonblocking STMs up to the level of being competitive with the state-of-the-art blocking STMs such as TL2.

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    cover image ACM Conferences
    PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
    February 2008
    308 pages
    ISBN:9781595937957
    DOI:10.1145/1345206
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 20 February 2008

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    Author Tags

    1. nonblocking
    2. software transactional memory

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    • (2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
    • (2021)ZeusProceedings of the Sixteenth European Conference on Computer Systems10.1145/3447786.3456234(145-161)Online publication date: 21-Apr-2021
    • (2020)Lock-free transactional vectorProceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/3380536.3380543(1-10)Online publication date: 22-Feb-2020
    • (2020)Nonblocking Persistent Software Transactional Memory2020 IEEE 27th International Conference on High Performance Computing, Data, and Analytics (HiPC)10.1109/HiPC50609.2020.00042(283-293)Online publication date: Dec-2020
    • (2017)Brief AnnouncementProceedings of the ACM Symposium on Principles of Distributed Computing10.1145/3087801.3087866(251-253)Online publication date: 25-Jul-2017
    • (2016)Optimizing memory transactions for large-scale programsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.12.00189:C(13-24)Online publication date: 1-Mar-2016
    • (2016)Wait-Free SynchronizationEncyclopedia of Algorithms10.1007/978-1-4939-2864-4_472(2345-2351)Online publication date: 22-Apr-2016
    • (2015)Queue-Based and Adaptive Lock Algorithms for Scalable Resource Allocation on Shared-Memory MultiprocessorsInternational Journal of Parallel Programming10.1007/s10766-014-0317-643:5(721-751)Online publication date: 1-Oct-2015
    • (2014)InvyswellProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628086(187-200)Online publication date: 24-Aug-2014
    • (2013)Boosting timestamp-based transactional memory by exploiting hardware cycle countersACM Transactions on Architecture and Code Optimization10.1145/2541228.255529710:4(1-21)Online publication date: 1-Dec-2013
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