research-article

Open access

Boosting timestamp-based transactional memory by exploiting hardware cycle counters

Authors:

Michael SpearAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, Issue 4

Article No.: 40, Pages 1 - 21

https://doi.org/10.1145/2541228.2555297

Published: 01 December 2013 Publication History

Abstract

Time-based transactional memories typically rely on a shared memory counter to ensure consistency. Unfortunately, such a counter can become a bottleneck. In this article, we identify properties of hardware cycle counters that allow their use in place of a shared memory counter. We then devise algorithms that exploit the x86 cycle counter to enable bottleneck-free transactional memory runtime systems. We also consider the impact of privatization safety and hardware ordering constraints on the correctness, performance, and generality of our algorithms.

References

[1]

Abadi, M., Birrell, A., Harris, T., and Isard, M. 2008. Semantics of transactional Memory and Automatic Mutual Exclusion. In Proceedings of the 35th ACM Symposium on Principles of Programming Languages.

Digital Library

[2]

Adl-Tabatabai, A.-R., Shpeisman, T., and Gottschlich, J. 2012. Draft specification of transactional language constructs for C++. Version 1.1. http://justingottschlich.com/tm-specification-for-c-v-1-1/.

[3]

Ansari, M., Kotselidis, C., Jarvis, K., Lujan, M., Kirkham, C., and Watson, I. 2008. Lee-TM: A Non-trivial Benchmark for Transactional Memory. In Proceedings of the International Conference on Algorithms and Architectures for Parallel Processing.

Digital Library

[4]

Dalessandro, L., Spear, M., and Scott, M. L. 2010. NOrec: Streamlining STM by Abolishing Ownership Records. In Proceedings of the 15th ACM Symposium on Principles and Practice of Parallel Programming. Bangalore, India.

Digital Library

[5]

Dice, D., Shalev, O., and Shavit, N. 2006. Transactional locking II. In Proceedings of the 20th International Symposium on Distributed Computing.

Digital Library

[6]

Dragojevic, A., Guerraoui, R., and Kapalka, M. 2009. Stretching transactional memory. In Proceedings of the 30th ACM Conference on Programming Language Design and Implementation. Dublin, Ireland.

Digital Library

[7]

Felber, P., Fetzer, C. and Riegel, T. 2008. Dynamic performance tuning of word-based software transactional memory. In Proceedings of the 13th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[8]

Fetzer, C. and Felber, P. 2007. Time-based transactional memory with scalable time bases. In Proceedings of the 19th ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[9]

Fraser, K. 2003. Practical Lock-Freedom. Ph.D. thesis. King’s College, University of Cambridge.

[10]

Guerraoui, R. and Kapalka, M. 2008. On the correctness of transactional memory. In Proceedings of the 13th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[11]

Harris, T., Larus, J., and Rajwar, R. 2010. Transactional Memory (2nd ed.). Synthesis Lectures on Computer Architecture. Morgan & Claypool.

Digital Library

[12]

Herlihy, M. P., Luchangco, V., Moir, M., and Scherer III, W. N. 2003. Software transactional memory for dynamic-sized data structures. In Proceedings of the 22nd ACM Symposium on Principles of Distributed Computing. Boston, MA.

Digital Library

[13]

Intel Corp. 2012. Intel 64 and IA-32 Architectures Software Developer’s Manual 325462-044US Ed. Intel Corp.

[14]

Marathe, V. and Moir, M. 2008. Toward high performance nonblocking software transactional memory. In Proceedings of the 13th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[15]

Marathe, V. J., Scherer III, W. N., and Scott, M. L. 2005. Adaptive software transactional memory. In Proceedings of the 19th International Symposium on Distributed Computing.

Digital Library

[16]

Marathe, V. J., Spear, M., Heriot, C., Acharya, A., Eisenstat, D., Scherer III, W. N., and Scott, M. L. 2006. Lowering the overhead of nonblocking software transactional memory. In Proceedings of the 1st ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing.

[17]

Marathe, V. J., Spear, M., and Scott, M. L. 2008. Scalable techniques for transparent privatization in software transactional memory. In Proceedings of the 37th International Conference on Parallel Processing.

Digital Library

[18]

Menon, V., Balensiefer, S., Shpeisman, T., Adl-Tabatabai, A.-R., Hudson, R., Saha, B., and Welc, A. 2008. Practical weak-atomicity semantics for Java STM. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[19]

Minh, C. C., Chung, J., Kozyrakis, C., and Olukotun, K. 2008. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the IEEE International Symposium on Workload Characterization.

[20]

Riegel, T., Fetzer, C. and Felber, P. 2006. Snapshot isolation for software transactional memory. In Proceedings of the 1st ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing.

[21]

Shavit, N. and Touitou, D. 1995. Software transactional memory. In Proceedings of the 14th ACM Symposium on Principles of Distributed Computing.

Digital Library

[22]

Shpeisman, T., Menon, V., Adl-Tabatabai, A.-R., Balensiefer, S., Grossman, D., Hudson, R. L., Moore, K., and Saha, B. 2007. Enforcing isolation and ordering in STM. In Proceedings of the 2007 ACM Conference on Programming Language Design and Implementation.

Digital Library

[23]

Spear, M. 2010. Lightweight, robust adaptivity for software transactional memory. In Proceedings of the 22nd ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

[24]

Spear, M., Dalessandro, L., Marathe, V. J., and Scott, M. L. 2008. Ordering-based semantics for aoftware transactional memory. In Proceedings of the 12th International Conference on Principles of Distributed Systems.

Digital Library

[25]

Spear, M., Dalessandro, L., Marathe, V. J., and Scott, M. L. 2009. A comprehensive strategy for contention management in software transactional memory. In Proceedings of the 14th ACM Symposium on Principles and Practice of Parallel Programming.

Digital Library

[26]

Spear, M., Marathe, V., Dalessandro, L., and Scott, M. 2007. Privatization techniques for software transactional memory (POSTER). In Proceedings of the 26th ACM Symposium on Principles of Distributed Computing.

Digital Library

[27]

Wang, C., Chen, W.-Y., Wu, Y., Saha, B., and Adl-Tabatabai, A.-R. 2007. Code generation and optimization for transactional memory constructs in an unmanaged language. In Proceedings of the 2007 International Symposium on Code Generation and Optimization.

Digital Library

[28]

Zhang, R., Budimlic, Z., and Scherer III, W. N. 2008. Commit phase in timestamp-based STM. In Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures.

Digital Library

Cited By

Kobus TKokoci?ski MWojciechowski PDhulipala LSun Y(2024)Jiffy: A Lock-free Skip List with Batch Updates and Snapshots (Abstract)Proceedings of the 2024 ACM Workshop on Highlights of Parallel Computing10.1145/3670684.3673410(5-7)Online publication date: 17-Jun-2024
https://dl.acm.org/doi/10.1145/3670684.3673410
Blelloch GWei YLee IChabbi MSteuwer M(2024)VERLIB: Concurrent Versioned PointersProceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming10.1145/3627535.3638501(200-214)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1145/3627535.3638501
Li YLiu HGao JZhang JGuan ZChen Z(2024)Accelerating block lifecycle on blockchain via hardware transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104779184(104779)Online publication date: Feb-2024
https://doi.org/10.1016/j.jpdc.2023.104779
Show More Cited By

Boosting timestamp-based transactional memory by exploiting hardware cycle counters
1. Computing methodologies
  1. Parallel computing methodologies

Recommendations

Safe privatization in transactional memory
PPoPP '18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

Transactional memory (TM) facilitates the development of concurrent applications by letting the programmer designate certain code blocks as atomic. Programmers using a TM often would like to access the same data both inside and outside transactions, ...
Safe privatization in transactional memory
PPoPP '18

Transactional memory (TM) facilitates the development of concurrent applications by letting the programmer designate certain code blocks as atomic. Programmers using a TM often would like to access the same data both inside and outside transactions, ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 10, Issue 4

December 2013

1046 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2541228

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 2013

Accepted: 01 November 2013

Revised: 01 October 2013

Received: 01 June 2013

Published in TACO Volume 10, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

21
Total Citations
View Citations
550
Total Downloads

Downloads (Last 12 months)104
Downloads (Last 6 weeks)27

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Kobus TKokoci?ski MWojciechowski PDhulipala LSun Y(2024)Jiffy: A Lock-free Skip List with Batch Updates and Snapshots (Abstract)Proceedings of the 2024 ACM Workshop on Highlights of Parallel Computing10.1145/3670684.3673410(5-7)Online publication date: 17-Jun-2024
https://dl.acm.org/doi/10.1145/3670684.3673410
Blelloch GWei YLee IChabbi MSteuwer M(2024)VERLIB: Concurrent Versioned PointersProceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming10.1145/3627535.3638501(200-214)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1145/3627535.3638501
Li YLiu HGao JZhang JGuan ZChen Z(2024)Accelerating block lifecycle on blockchain via hardware transactional memoryJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104779184(104779)Online publication date: Feb-2024
https://doi.org/10.1016/j.jpdc.2023.104779
Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Grimes ONelson-Slivon JHassan APalmieri R(2023)Opportunities and Limitations of Hardware Timestamps in Concurrent Data Structures2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS54959.2023.00068(624-634)Online publication date: May-2023
https://doi.org/10.1109/IPDPS54959.2023.00068
Kobus TKokociński MWojciechowski PLee JAgrawal KSpear M(2022)JiffyProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508437(400-415)Online publication date: 2-Apr-2022
https://dl.acm.org/doi/10.1145/3503221.3508437
Giles EDoshi KVarman PJacob B(2018)Hardware transactional persistent memoryProceedings of the International Symposium on Memory Systems10.1145/3240302.3240305(190-205)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240305
Mohamedin MPeluso SKishi MHassan APalmieri R(2018)NemoProceedings of the 47th International Conference on Parallel Processing10.1145/3225058.3225123(1-10)Online publication date: 13-Aug-2018
https://dl.acm.org/doi/10.1145/3225058.3225123
Kashyap SMin CKim KKim TOliveira RFelber PHu Y(2018)A scalable ordering primitive for multicore machinesProceedings of the Thirteenth EuroSys Conference10.1145/3190508.3190510(1-15)Online publication date: 23-Apr-2018
https://dl.acm.org/doi/10.1145/3190508.3190510
Nguyen DPingali K(2017)What Scalable Programs Need from Transactional MemoryACM SIGARCH Computer Architecture News10.1145/3093337.303775045:1(105-118)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037750
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents