research-article

Hardware transactional persistent memory

Authors:

Peter VarmanAuthors Info & Claims

MEMSYS '18: Proceedings of the International Symposium on Memory Systems

Pages 190 - 205

https://doi.org/10.1145/3240302.3240305

Published: 01 October 2018 Publication History

Abstract

Emerging Persistent Memory technologies (also pm, Non-Volatile DIMMs, Storage Class Memory or scm) hold tremendous promise for accelerating popular data-management applications like in-memory databases. However, programmers now need to deal with ensuring the atomicity of transactions on Persistent Memory resident data and maintaining consistency between the order in which processors perform stores and that in which the updated values become durable.

The problem is specially challenging when high-performance isolation mechanisms like Hardware Transactional Memory (htm) are used for concurrency control. This work shows how htm transactions can be ordered correctly and atomically into PM by the use of a novel software protocol combined with a Persistent Memory Controller, without requiring changes to processor cache hardware or htm protocols. In contrast, previous approaches require significant changes to existing processor microarchitectures. Our approach, evaluated using both micro-benchmarks and the stamp suite compares well with standard (volatile) htm transactions. It also yields significant gains in throughput and latency in comparison with persistent transactional locking.

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Cited By

Grimes ONelson-Slivon JHassan APalmieri R(2023)Opportunities and Limitations of Hardware Timestamps in Concurrent Data Structures2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS54959.2023.00068(624-634)Online publication date: May-2023
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Kobus TKokociński MWojciechowski PLee JAgrawal KSpear M(2022)JiffyProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508437(400-415)Online publication date: 2-Apr-2022
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Baldassin ABarreto JCastro DRomano P(2021)Persistent MemoryACM Computing Surveys10.1145/346540254:7(1-37)Online publication date: 18-Jul-2021
https://dl.acm.org/doi/10.1145/3465402
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Hardware transactional persistent memory

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cover image ACM Other conferences

MEMSYS '18: Proceedings of the International Symposium on Memory Systems

October 2018

361 pages

ISBN:9781450364751

DOI:10.1145/3240302

General Chair:
Bruce Jacob
University of Maryland

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 October 2018

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MEMSYS '18

MEMSYS '18: The International Symposium on Memory Systems

October 1 - 4, 2018

Virginia, Alexandria, USA

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Cited By

Grimes ONelson-Slivon JHassan APalmieri R(2023)Opportunities and Limitations of Hardware Timestamps in Concurrent Data Structures2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS54959.2023.00068(624-634)Online publication date: May-2023
https://doi.org/10.1109/IPDPS54959.2023.00068
Kobus TKokociński MWojciechowski PLee JAgrawal KSpear M(2022)JiffyProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508437(400-415)Online publication date: 2-Apr-2022
https://dl.acm.org/doi/10.1145/3503221.3508437
Baldassin ABarreto JCastro DRomano P(2021)Persistent MemoryACM Computing Surveys10.1145/346540254:7(1-37)Online publication date: 18-Jul-2021
https://dl.acm.org/doi/10.1145/3465402
Romano PBourcier JJiang ZBezemer CCortellessa V(2021)Transactions in the Era of Non Volatile Memory and Heterogeneous Memory ArchitecturesCompanion of the ACM/SPEC International Conference on Performance Engineering10.1145/3447545.3451904(93-94)Online publication date: 19-Apr-2021
https://dl.acm.org/doi/10.1145/3447545.3451904
Shull TVougioukas INikoleris NElsasser WTorrellas JMartínez JDuato JJohn L(2021)Execution dependence extension (EDE)Proceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00043(456-469)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00043
Alshboul MRamrakhyani PWang WTuck JSolihin Y(2021)BBB: Simplifying Persistent Programming using Battery-Backed Buffers2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00019(111-124)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00019

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