Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-XACT standards and demonstrate how these standards are deployed in three industrial IP integration flows. Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e. IP-XACT based verification software generation and IP-XACT based configuration of debug environments. We conclude that IP-XACT is enabling powerful IP integration methodologies and that future extensions can further increase the effectiveness of IP-XACT standards.

References

[1]

O. Florent et al., "Spirit-based IP Assembly and SDC Promotion for a 65-nm System-on-Chip using coreAssembler", in Proceedings of SNUG Europe 2006.

Google Scholar

[2]

O. Florent and F. Remond, "65nm SOC design based on an emerging standard: Spirit", presented at IP-SOC 2005.

Google Scholar

[3]

F. Ghenassia, Ed., Transaction-Level Modeling with SystemC:TLM Concepts and Applications for Embedded Systems, Springer, 2005.

Digital Library

Google Scholar

[4]

Geoff Mole et al, "Philips Semiconductors Next Generation Architectural IP ReUse Developments for SoC Integration", IP-SoC 2004.

Google Scholar

[5]

Strik, Marino et al," Subsystem Exchange in a Concurrent Design Process Environment", Proceedings DATE 2008.

Digital Library

Google Scholar

Cited By

View all

Ammar MBaklouti MPelcat MDesnos KAbid M(2018)Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCsJournal of Signal Processing Systems10.5555/3200212.320022290:4(537-570)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.5555/3200212.3200222
Jassi MHu YMueller-Gritschneder DSchlichtmann U(2018)Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCsACM Transactions on Design Automation of Electronic Systems10.1145/313938123:3(1-26)Online publication date: 11-Apr-2018
https://dl.acm.org/doi/10.1145/3139381
Fezzardi PFerrandi FPilato C(2018)Enabling Automated Bug Detection for IP-Based Designs Using High-Level SynthesisIEEE Design & Test10.1109/MDAT.2018.282412135:5(54-62)Online publication date: Oct-2018
https://doi.org/10.1109/MDAT.2018.2824121
Show More Cited By

Index Terms

Industrial IP integration flows based on IP-XACT™ standards
1. Hardware

Recommendations

A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow
CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

We present a reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT standard. The test infrastructure is configurable, meaning that specific configurations can be generated from a ...
IP-XACT extensions for Reconfigurable Computing
ASAP '11: Proceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors

Many of today's embedded multiprocessor systems are implemented as heterogeneous systems, consisting of hardware and software components. To automate the composition and integration of multiprocessor systems, the IP-XACT standard was defined to describe ...
A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven ...

Comments

Information & Contributors

Information

Published In

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

DATE '08

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

Munich, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

16
Total Citations
View Citations
485
Total Downloads

Downloads (Last 12 months)13
Downloads (Last 6 weeks)3

Reflects downloads up to 06 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Ammar MBaklouti MPelcat MDesnos KAbid M(2018)Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCsJournal of Signal Processing Systems10.5555/3200212.320022290:4(537-570)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.5555/3200212.3200222
Jassi MHu YMueller-Gritschneder DSchlichtmann U(2018)Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCsACM Transactions on Design Automation of Electronic Systems10.1145/313938123:3(1-26)Online publication date: 11-Apr-2018
https://dl.acm.org/doi/10.1145/3139381
Fezzardi PFerrandi FPilato C(2018)Enabling Automated Bug Detection for IP-Based Designs Using High-Level SynthesisIEEE Design & Test10.1109/MDAT.2018.282412135:5(54-62)Online publication date: Oct-2018
https://doi.org/10.1109/MDAT.2018.2824121
Kashai Y(2016)SoC Block-Based Design and IP AssemblyElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-8(75-84)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19569-8
Goswami PSrirangapathi SMatad CLiu S(2016)Re-target-able software power management framework using SoC data auto-generationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898085(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898085
Jassi MMüller-Gritschneder DSchlichtmann U(2015)GRIPProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744845(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744845
Ma MHedrich LSporrer C(2014)ASDeXDesign Automation for Embedded Systems10.1007/s10617-012-9088-818:1-2(99-118)Online publication date: 1-Mar-2014
https://dl.acm.org/doi/10.1007/s10617-012-9088-8
Vermeulen BGoossens KVermeulen BGoossens K(2014)Related WorkDebugging Systems-on-Chip10.1007/978-3-319-06242-6_9(235-255)Online publication date: 15-Jul-2014
https://doi.org/10.1007/978-3-319-06242-6_9
Neely CBrebner GShang W(2013)ReShapeACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574486:1(1-23)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1145/2457443.2457448
Liu HPetracca MCarloni LRosenstiel WMacii E(2012)Compositional system-level design exploration with planning of high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492870(641-646)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492870
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

IP-XACT extensions for Reconfigurable Computing

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

IP-XACT extensions for Reconfigurable Computing

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations