Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-XACT standards and demonstrate how these standards are deployed in three industrial IP integration flows. Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e. IP-XACT based verification software generation and IP-XACT based configuration of debug environments. We conclude that IP-XACT is enabling powerful IP integration methodologies and that future extensions can further increase the effectiveness of IP-XACT standards.

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Ammar MBaklouti MPelcat MDesnos KAbid M(2018)Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCsJournal of Signal Processing Systems10.5555/3200212.320022290:4(537-570)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.5555/3200212.3200222
Jassi MHu YMueller-Gritschneder DSchlichtmann U(2018)Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCsACM Transactions on Design Automation of Electronic Systems10.1145/313938123:3(1-26)Online publication date: 11-Apr-2018
https://dl.acm.org/doi/10.1145/3139381
Fezzardi PFerrandi FPilato C(2018)Enabling Automated Bug Detection for IP-Based Designs Using High-Level SynthesisIEEE Design & Test10.1109/MDAT.2018.282412135:5(54-62)Online publication date: Oct-2018
https://doi.org/10.1109/MDAT.2018.2824121
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Industrial IP integration flows based on IP-XACT™ standards
1. Hardware

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DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

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Ammar MBaklouti MPelcat MDesnos KAbid M(2018)Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCsJournal of Signal Processing Systems10.5555/3200212.320022290:4(537-570)Online publication date: 1-Apr-2018
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Fezzardi PFerrandi FPilato C(2018)Enabling Automated Bug Detection for IP-Based Designs Using High-Level SynthesisIEEE Design & Test10.1109/MDAT.2018.282412135:5(54-62)Online publication date: Oct-2018
https://doi.org/10.1109/MDAT.2018.2824121
Kashai Y(2016)SoC Block-Based Design and IP AssemblyElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-8(75-84)Online publication date: 14-Apr-2016
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Goswami PSrirangapathi SMatad CLiu S(2016)Re-target-able software power management framework using SoC data auto-generationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898085(1-6)Online publication date: 5-Jun-2016
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Ma MHedrich LSporrer C(2014)ASDeXDesign Automation for Embedded Systems10.1007/s10617-012-9088-818:1-2(99-118)Online publication date: 1-Mar-2014
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Vermeulen BGoossens KVermeulen BGoossens K(2014)Related WorkDebugging Systems-on-Chip10.1007/978-3-319-06242-6_9(235-255)Online publication date: 15-Jul-2014
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Liu HPetracca MCarloni LRosenstiel WMacii E(2012)Compositional system-level design exploration with planning of high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492870(641-646)Online publication date: 12-Mar-2012
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A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

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