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Synthesis of reconfigurable high-performance multicore systems

Published: 22 February 2009 Publication History

Abstract

Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerating system performance, lowering power consumption and minimizing operation cost. In order to achieve high performance on this hybrid system, it is important to effectively explore the design space, which includes accelerator synthesis, resource allocation and job scheduling. In this paper we propose novel algorithms for reconfigurable resource allocation and job scheduling to optimize performance of multicore RHPC systems. Specifically, we first propose an interesting approximation algorithm to assign jobs to processors with consideration of coprocessors at the global optimization step. Then we present an optimal solution for coprocessor selection in the local optimization step. In this paper we also demonstrate that designers can quickly explore a large number of accelerator design choices with the help of high-level synthesis tools. Experiments show that our proposed techniques provide efficient solutions for real-life benchmarks and generate higher quality of results. When compared to other heuristic algorithms, our results can achieve up to 47% performance improvement.

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Cited By

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  • (2015)Automating Elimination of Idle Functions by Runtime ReconfigurationACM Transactions on Reconfigurable Technology and Systems10.1145/27004158:3(1-28)Online publication date: 11-May-2015
  • (2015)The Aladdin Approach to Accelerator Design and ModelingIEEE Micro10.1109/MM.2015.5035:3(58-70)Online publication date: May-2015
  • (2014)AladdinProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665689(97-108)Online publication date: 14-Jun-2014
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  1. Synthesis of reconfigurable high-performance multicore systems

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      cover image ACM Conferences
      FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
      February 2009
      302 pages
      ISBN:9781605584102
      DOI:10.1145/1508128
      • General Chair:
      • Paul Chow,
      • Program Chair:
      • Peter Cheung
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 22 February 2009

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      Author Tags

      1. coprocessor synthesis
      2. design space exploration
      3. reconfigurable high-performance computing

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      Cited By

      View all
      • (2015)Automating Elimination of Idle Functions by Runtime ReconfigurationACM Transactions on Reconfigurable Technology and Systems10.1145/27004158:3(1-28)Online publication date: 11-May-2015
      • (2015)The Aladdin Approach to Accelerator Design and ModelingIEEE Micro10.1109/MM.2015.5035:3(58-70)Online publication date: May-2015
      • (2014)AladdinProceeding of the 41st annual international symposium on Computer architecuture10.5555/2665671.2665689(97-108)Online publication date: 14-Jun-2014
      • (2014)AladdinACM SIGARCH Computer Architecture News10.1145/2678373.266568942:3(97-108)Online publication date: 14-Jun-2014
      • (2014)Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)10.1109/ISCA.2014.6853196(97-108)Online publication date: Jun-2014
      • (2014)MachSuite: Benchmarks for accelerator design and customized architectures2014 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2014.6983050(110-119)Online publication date: Oct-2014
      • (2014)Multi-accelerator system development with the ShrinkFit acceleration framework2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974665(75-82)Online publication date: Oct-2014
      • (2013)Quantifying accelerationProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648759(395-400)Online publication date: 4-Sep-2013
      • (2013)Automating resource optimisation in reconfigurable design (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435338(275-275)Online publication date: 11-Feb-2013
      • (2013)Shrink-FitIEEE Computer Architecture Letters10.1109/L-CA.2012.712:1(17-20)Online publication date: 1-Jan-2013
      • Show More Cited By

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