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Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

Authors:

Daniele Ludovici,

Georgi Nedeltchev Gaydadjiev,

Davide Bertozzi,

Luca BeniniAuthors Info & Claims

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI

Pages 125 - 128

https://doi.org/10.1145/1531542.1531574

Published: 10 May 2009 Publication History

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Abstract

In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power implications, but gives rise to a well-differentiated point in the architecture design space. This in an effect of the tight interaction existing between architecture and physical design layers in nanoscale technologies.

This work assesses several NoC link inference techniques (buffering options, link pipelining) by means of commercial backend synthesis tools, taking the system-level perspective. In fact, performance speed-ups and power overhead are not evaluated for the links in isolation but for the network topology as a whole, thus showing their sensitivity to the link inference strategy. k-ary n-mesh topologies are considered for the sake of analysis, in that they provide a range of topologies with increasing total wirelength.

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Cited By

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Abellán JFernández JAcacio MBertozzi DBortolotti DMarongiu ABenini LRosenstiel WMacii E(2012)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492831(491-496)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492831
Abellan JFernandez JAcacio MBertozzi DBortolotti DMarongiu ABenini L(2012)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176519(491-496)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176519
Bertozzi DStrano ALudovici DGilabert F(2012)Technology‐Aware Communication Architecture Design for Parallel Hardware PlatformsAdvanced Circuits for Emerging Technologies10.1002/9781118181508.ch14(353-392)Online publication date: 7-May-2012
https://doi.org/10.1002/9781118181508.ch14
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Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
1. Hardware

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Information & Contributors

Information

Published In

GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI

May 2009

558 pages

ISBN:9781605585222

DOI:10.1145/1531542

Co-chair:
Fabrizio Lombardi,
General Chairs:
Sanjukta Bhanja
University of South Florida, USA
,
Yehia Massoud
Rice University, USA
,
Program Chair:
R. Iris Bahar
Brown University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 May 2009

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GLSVLSI '09

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GLSVLSI '09: Great Lakes Symposium on VLSI 2009

May 10 - 12, 2009

MA, Boston Area, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Abellán JFernández JAcacio MBertozzi DBortolotti DMarongiu ABenini LRosenstiel WMacii E(2012)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492831(491-496)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492831
Abellan JFernandez JAcacio MBertozzi DBortolotti DMarongiu ABenini L(2012)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176519(491-496)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176519
Bertozzi DStrano ALudovici DGilabert F(2012)Technology‐Aware Communication Architecture Design for Parallel Hardware PlatformsAdvanced Circuits for Emerging Technologies10.1002/9781118181508.ch14(353-392)Online publication date: 7-May-2012
https://doi.org/10.1002/9781118181508.ch14
(2011)BibliographyDesigning Network On-Chip Architectures in the Nanoscale Era10.1201/b10477-18(443-475)Online publication date: 9-Feb-2011
https://doi.org/10.1201/b10477-18
Ferraresi MGobbo GLudovici DBertozzi D(2011)Bringing Network-on-Chip links to 45nm2011 International Symposium on System on Chip (SoC)10.1109/ISSOC.2011.6089686(122-127)Online publication date: Oct-2011
https://doi.org/10.1109/ISSOC.2011.6089686
Strano ALudovici DBertozzi D(2010)A library of dual-clock FIFOs for cost-effective and flexible MPSoC design2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/ICSAMOS.2010.5642098(20-27)Online publication date: Jul-2010
https://doi.org/10.1109/ICSAMOS.2010.5642098
Ludovici DStrano ABertozzi DPalesi MKumar S(2009)Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switchesProceedings of the 2nd International Workshop on Network on Chip Architectures10.1145/1645213.1645222(31-36)Online publication date: 12-Dec-2009
https://dl.acm.org/doi/10.1145/1645213.1645222

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