research-article

Simulation and SAT-based Boolean matching for large Boolean networks

Authors:

Chung-Ming Chan,

Jung-Chang LiuAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 396 - 401

https://doi.org/10.1145/1629911.1630016

Published: 26 July 2009 Publication History

Abstract

Boolean matching is to check the equivalence of two target functions under input permutation and input/output phase assignment. This paper addresses the permutation independent (P-equivalent) Boolean matching problem. We will propose a matching algorithm seamlessly integrating Simulation and Boolean Satisfiability (S&S) techniques. Our proposed algorithm will first utilize functional properties like unateness and symmetry to reduce the searching space. In the followed simulation phase, three types of input vector generation and checking method will be used to match the inputs of two target functions. Experimental results on large benchmarking circuits demonstrate that our matching algorithm is indeed very effective and efficient to solve Boolean matching for large Boolean networks.

References

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Cited By

Chou CHsu CWu CTu KKhoo K(2023)Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323797(1-4)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323797
Zhang JGuo WYang GZhu YLv X(2022)A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon DecompositionIEEE Access10.1109/ACCESS.2022.322176410(120369-120382)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3221764
Zhou XWang LMishchenko A(2019)Fast Adjustable NPN Classification Using Generalized SymmetriesACM Transactions on Reconfigurable Technology and Systems10.1145/331391712:2(1-16)Online publication date: 12-Apr-2019
https://dl.acm.org/doi/10.1145/3313917
Show More Cited By

Index Terms

Simulation and SAT-based Boolean matching for large Boolean networks
1. Hardware
  1. Hardware validation
    1. Functional verification

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cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 July 2009

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National Science Council Taiwan

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DAC '09

Sponsor:

EDAC
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IEEE-CAS

DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chou CHsu CWu CTu KKhoo K(2023)Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323797(1-4)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323797
Zhang JGuo WYang GZhu YLv X(2022)A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon DecompositionIEEE Access10.1109/ACCESS.2022.322176410(120369-120382)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3221764
Zhou XWang LMishchenko A(2019)Fast Adjustable NPN Classification Using Generalized SymmetriesACM Transactions on Reconfigurable Technology and Systems10.1145/331391712:2(1-16)Online publication date: 12-Apr-2019
https://dl.acm.org/doi/10.1145/3313917
Zhang JYang GHung WWu JZhu Y(2018)A New Pairwise NPN Boolean Matching Algorithm Based on Structural Difference SignatureSymmetry10.3390/sym1101002711:1(27)Online publication date: 29-Dec-2018
https://doi.org/10.3390/sym11010027
Zhang JYang GHung WWu J(2017)A Canonical-Based NPN Boolean Matching Algorithm Utilizing Boolean Difference and Cofactor SignatureIEEE Access10.1109/ACCESS.2017.27783385(27777-27785)Online publication date: 2017
https://doi.org/10.1109/ACCESS.2017.2778338
Yuan KKuo CJiang JLi MHenkel J(2013)Encoding multi-valued functions for symmetryProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561977(771-778)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561977
Hsu CLin WWang HLu FKhoo KHenkel J(2013)ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suiteProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561882(265-267)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561882
Huang SLin WHuang PHuang C(2013)Match and ReplaceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.222645632:3(467-478)Online publication date: 1-Mar-2013
https://dl.acm.org/doi/10.1109/TCAD.2012.2226456
Yuan KKuo CJiang JLi M(2013)Encoding multi-valued functions for symmetry2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691201(771-778)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691201
Hsu CLin WWang HLu FKhoo K(2013)ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691129(265-267)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691129
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