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Power-driven flip-flop merging and relocation

Published: 27 March 2011 Publication History

Abstract

We propose a power-driven flip-flop merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption, as well as the switching power of the nets connected to the flip-flops by selectively merging flip-flops into multi-bit flip-flops and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the clock wirelength by 30 to 50%. Meanwhile, the switching power of signal nets connected to the flip-flops were reduced by 2 to 43%.

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Cited By

View all
  • (2025)Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing AwarenessProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697725(1230-1236)Online publication date: 20-Jan-2025
  • (2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
  • (2019)Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309753(11-18)Online publication date: 4-Apr-2019
  • Show More Cited By

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cover image ACM Conferences
ISPD '11: Proceedings of the 2011 international symposium on Physical design
March 2011
192 pages
ISBN:9781450305501
DOI:10.1145/1960397
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 27 March 2011

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Author Tags

  1. clock network
  2. low power
  3. multi-bit flip-flop
  4. post placement

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  • Research-article

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ISPD'11
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ISPD'11: International Symposium on Physical Design
March 27 - 30, 2011
CA, Santa Barbara, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25
International Symposium on Physical Design
March 16 - 19, 2025
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Cited By

View all
  • (2025)Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing AwarenessProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697725(1230-1236)Online publication date: 20-Jan-2025
  • (2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
  • (2019)Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309753(11-18)Online publication date: 4-Apr-2019
  • (2019)Post-Placement Power Optimization With Multi-Bit Flip-FlopsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216571630:12(1870-1882)Online publication date: 3-Jan-2019
  • (2018)Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low PowerInternational Journal of Electrical and Electronics Research10.37391/IJEER.0602046:2(32-36)Online publication date: 25-May-2018
  • (2014)A high speed proficient power reduction method using clustering based flip flop merging2014 International Conference on Communication and Signal Processing10.1109/ICCSP.2014.6950084(1424-1429)Online publication date: Apr-2014
  • (2013)Slack budgeting and slack to length converting for multi-bit flip-flop mergingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485721(1837-1842)Online publication date: 18-Mar-2013
  • (2013)Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flopi-manager's Journal on Circuits and Systems10.26634/jcir.1.4.25931:4(22-26)Online publication date: 15-Nov-2013
  • (2013)Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimizationACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148418:3(1-20)Online publication date: 29-Jul-2013
  • (2013)FF-bondProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451955(147-153)Online publication date: 24-Mar-2013
  • Show More Cited By

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