research-article

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization

Authors:

Sean Shih-Ying Liu,

Hung-Ming ChenAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 3

Article No.: 40, Pages 1 - 20

https://doi.org/10.1145/2491477.2491484

Published: 29 July 2013 Publication History

Abstract

In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.

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Cited By

Hsieh YLin TChang YWu HJiang I(2025)Graceful Register Clustering and Rebanking for Power and Timing BalancingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344823344:3(1070-1083)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3448233
Hyun DKoh SJung YKim TShin Y(2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
https://doi.org/10.1145/3573387
Chang YLin TJiang INam GBustany ISwartz W(2019)Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309753(11-18)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3299902.3309753
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Index Terms

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 18, Issue 3

July 2013

268 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2491477

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 July 2013

Accepted: 01 January 2013

Revised: 01 October 2012

Received: 01 July 2012

Published in TODAES Volume 18, Issue 3

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Cited By

Hsieh YLin TChang YWu HJiang I(2025)Graceful Register Clustering and Rebanking for Power and Timing BalancingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344823344:3(1070-1083)Online publication date: Mar-2025
https://doi.org/10.1109/TCAD.2024.3448233
Hyun DKoh SJung YKim TShin Y(2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
https://doi.org/10.1145/3573387
Chang YLin TJiang INam GBustany ISwartz W(2019)Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3309753(11-18)Online publication date: 4-Apr-2019
https://dl.acm.org/doi/10.1145/3299902.3309753
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navette LChinnery D(2019)Timing-Driven and Placement-Aware Multibit Register CompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285274038:8(1501-1514)Online publication date: Aug-2019
https://doi.org/10.1109/TCAD.2018.2852740
Lee TPan DYang J(2018)Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing ConstraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269802537:1(245-256)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2698025
Seitanidis IDimitrakopoulos GMattheakis PMasse-Navete LChinnery D(2017)Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062327(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062327
Gluzer DWimer S(2017)Probability-Driven Multibit Flip-Flop Integration With Clock GatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.261400425:3(1173-1177)Online publication date: Mar-2017
https://doi.org/10.1109/TVLSI.2016.2614004
Hsu CHashimoto MLin M(2017)Minimizing detection-to-boosting latency toward low-power error-resilient circuitsIntegration10.1016/j.vlsi.2017.01.00258(236-244)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2017.01.002
Hsu CLin MHashimoto MTaskin BHo T(2016)Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient CircuitsProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947364(1-6)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947364
Arumugam SViswanaathan L(2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
https://doi.org/10.1002/cta.2277
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