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Efficient design space exploration for component-based system design

Published: 05 November 2012 Publication History

Abstract

As the technology scaling down continues to go beyond 22nm, the increasing transistor density on a single die is leading towards more and more complex systems-on-chip. Designers are faced with the challenge of how to efficiently design such a complicated system with tight time-to-market constraints. Component-based system design and design space exploration are two key techniques to overcoming the challenge. In this paper, we model the design space exploration of a system with difference constraints as a bi-criteria convex cost flow problem and develop an efficient solver for it based on parametric simplex method. Furthermore, considering the high cost of synthesizing the underlying soft IP cores, we propose an online algorithm to incrementally refine the system-level Pareto curves as more component-wise sampling points are added. The experimental results demonstrate the efficiency and effectiveness of the proposed algorithms.

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Cited By

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  • (2018)IP-enabled C/C++ based high level synthesisInternational Journal of Reconfigurable Computing10.1155/2014/4187502014(1-1)Online publication date: 13-Dec-2018
  • (2014)Recovery-based resilient latency-insensitive systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616733(1-6)Online publication date: 24-Mar-2014
  • (2013)Resource-constrained high-level datapath optimization in ASIP designProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485339(198-201)Online publication date: 18-Mar-2013

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cover image ACM Conferences
ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
November 2012
781 pages
ISBN:9781450315739
DOI:10.1145/2429384
  • General Chair:
  • Alan J. Hu
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2012

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Cited By

View all
  • (2018)IP-enabled C/C++ based high level synthesisInternational Journal of Reconfigurable Computing10.1155/2014/4187502014(1-1)Online publication date: 13-Dec-2018
  • (2014)Recovery-based resilient latency-insensitive systemsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616733(1-6)Online publication date: 24-Mar-2014
  • (2013)Resource-constrained high-level datapath optimization in ASIP designProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485339(198-201)Online publication date: 18-Mar-2013

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