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Techniques to improve performance in requester-wins hardware transactional memory

Authors:

Adrià Armejach,

Ruben Titos-Gil,

Osman S. Unsal,

Adrián CristalAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, Issue 4

Article No.: 42, Pages 1 - 25

https://doi.org/10.1145/2541228.2555299

Published: 01 December 2013 Publication History

Abstract

The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques—two software-based that employ information provided by the hardware and two that require simple core-local hardware additions—which have the potential to boost the performance of requester-wins HTM designs substantially.

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Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Nicolás-Conesa VTitos-Gil RFernández-Pascual RRos AAcacio M(2024)On the interactions between ILP and TLP with hardware transactional memoryMicroprocessors and Microsystems10.1016/j.micpro.2023.104975104(104975)Online publication date: Feb-2024
https://doi.org/10.1016/j.micpro.2023.104975
Fu CWan LHan J(2022)LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict ManagerIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.320677733:12(4849-4862)Online publication date: 1-Dec-2022
https://dl.acm.org/doi/10.1109/TPDS.2022.3206777
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Techniques to improve performance in requester-wins hardware transactional memory

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 10, Issue 4

December 2013

1046 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2541228

Issue’s Table of Contents

Copyright © 2013 ACM.

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Publication History

Published: 01 December 2013

Accepted: 01 November 2013

Revised: 01 September 2013

Received: 01 June 2013

Published in TACO Volume 10, Issue 4

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Swedish Foundation for Strategic Research
cooperation agreement between the Barcelona Supercomputing Center and Microsoft Research
European Cooperation in Science and Technology
Federación Española de Enfermedades Raras
Ministerio de Economía y Competitividad
Seventh Framework Programme

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Cited By

Wan LChao FLi QHan J(2024)LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00081(865-875)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPS57955.2024.00081
Nicolás-Conesa VTitos-Gil RFernández-Pascual RRos AAcacio M(2024)On the interactions between ILP and TLP with hardware transactional memoryMicroprocessors and Microsystems10.1016/j.micpro.2023.104975104(104975)Online publication date: Feb-2024
https://doi.org/10.1016/j.micpro.2023.104975
Fu CWan LHan J(2022)LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict ManagerIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.320677733:12(4849-4862)Online publication date: 1-Dec-2022
https://dl.acm.org/doi/10.1109/TPDS.2022.3206777
Titos-Gil RFernandez Pascual RRos AAcacio M(2021)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.3085210(1-1)Online publication date: 2021
https://doi.org/10.1109/TPDS.2021.3085210
Jeong JHong JMaeng SJung CKwon Y(2020)Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00051(525-538)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00051
Alistarh DHaider SKübler RNadiradze GScheideler CFineman J(2018)The Transactional Conflict ProblemProceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures10.1145/3210377.3210406(383-392)Online publication date: 11-Jul-2018
https://dl.acm.org/doi/10.1145/3210377.3210406
Dice DHerlihy MKogan A(2018)Improving Parallelism in Hardware Transactional MemoryACM Transactions on Architecture and Code Optimization10.1145/317796215:1(1-24)Online publication date: 22-Mar-2018
https://dl.acm.org/doi/10.1145/3177962
Park SPrvulovic MHughes C(2016)PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446072(285-296)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446072

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