Article

Free access

An efficient implementation of reactivity for modeling hardware in the scenic design environment

Authors:

Rajesh GuptaAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 70 - 75

https://doi.org/10.1145/266021.266037

Published: 13 June 1997 Publication History

Abstract

Reactivity is one of the key features of hardwaredescription languages. We present an efficient implementationof reactivity in the Scenic framework that allows the systemdesigner to model hardware blocks. Scenic allows the designerto use C++ to model mixed hardware-software systems witha C++ compiler and a small library and without the need ofa complex event-driven run-time kernel often found embeddedin hardware description languages (HDL) such as VHDL andVerilog. Moreover, Scenic hardware descriptions can be easilymapped to HDL and synthesized into hardware implementationsusing commercially available tools.In this paper we present Scenic's implementation of concurrency(signals and processes) and reactivity (waiting andwatching). When C++ is used as an HDL, context-switchingoverhead can become a significant performance issue duringsimulation. We introduce the notion of delayed expressionobjects, orlambdas, to reduce context-switching. Examplesand experimental results are presented to show the utility andsimulation efficiency using the Scenic framework.

References

[1]

M.A. Ardis, J. A. Chaves, L. J. Jagadeesan, R Mataga, C. Puchol, M. G. Staskauskas, and J. von Olnhausen. A Framework for Evaluating Specification Methods for Reactive Systems. IEEE Transactions on Software Engineering, 22(6):378-389, June 1996.

Digital Library

[2]

G. Berry. Real-time programming: General purpose or specialpurpose languages. In G. Ritter, editor, Information Processing 89, pages 11-17. Elsevier Science Publishers B.V. (North Holland), 1989.

[3]

G. Berry. Preemption in concurrent systems. In Proc. FSTTCS'93, Lecture Notes in Computer Science, volume 761, pages 72-93. Springer-Verlag, 1993.

Digital Library

[4]

G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science Of Computer Programming, 19(2):87-152, 1992.

Digital Library

[5]

R. Ernst, J. Henkel, and T. Benner. Hardware-Software Cosynthesis for Microcontrollers. IEEE Design & Test of Computers, pages 64-75, December 1993.

Digital Library

[6]

F. Balarin et al. Polis: A Design Environment for Control-Dominated Embedded Systems. See http://wwwcad.eecs.berkeley.edu/R espep/R esearch/hsc/abstract.html.

[7]

R.K. Gupta and G. De Micheli. A Co-Synthesis Approach to Embedded System Design Automation. Design Automation for Embedded Systems, 1 (1-2), January 1996.

Digital Library

[8]

C. Hansen. Hardware logic simulation by compilation. In Proceedings of the Design Automation Conference, pages 712-715, 1988.

Digital Library

[9]

A. Kalavade and E. A. Lee. A Hardware-Software Codesign Methodology for DSP Applications. IEEE Design & Test of Computeres, pages 16-28, September 1993.

Digital Library

[10]

D. Keppel. Tools and techniques for writing fast portable threads packages. Technical Report UW-CSE-93-05-06, University of Washington, 1993. Available atftp://ftp.cs.washington.edu:/tr.

[11]

D. Knapp. Behaviroal Synthesis: Digital System Design Using the Synopsys Behavioral Compiler. Prentice Hall, Upper Saddle River, NJ, 1996.

Digital Library

[12]

S. Kumar, J. H. Aylor, B. W. Johnson, and W. A. Wulf. Objectoriented techniques in hardware design. Computer, 27(6):64-70, June 1994.

Digital Library

[13]

R. P. Kurshan. Reducibility in analysis of coordination. LNCS, 103:19-39, 1987.

[14]

Teresa H. Meng. Synchronization Design for Digital Systems, chapter Synthesis of Self-Timed Circuits, pages 23-63. Kluwer Academic Publishers, 1991.

[15]

K. Olukotun and R. Helaihel. Automating architectural exploration with a fast simulator. In Notes of the Workshop on Hardware-Software Co-design, 1993.

[16]

J.E. Stoy. Denotational Semantics. MIT Press, Cambridge, MA, 1977.

[17]

D. E. Thomas, J. K. Adams, and H. Schmit. A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers, pages 6-15, September 1993.

Digital Library

[18]

M. Tremblay, G. Maturana, A. Inoue, and L. Kohn. A fast and flexible performance simulator for micro-architecture tradeoff analysis on UltraSPARCTM-I. In Proceedings of the Design Automation Conference, pages 2-6, June 1995.

Digital Library

[19]

W. Wolf. Hardware-Software Co-design of Embedded Systems. IEEE Proceedings, 82(7):965-989, July 1994.

Cited By

Kogel T(2022)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-15-6401-7_44-1(1-41)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_44-1
Lohstroh MRomeo ÍGoens ADerler PCastrillon JLee ESangiovanni-Vincentelli A(2020)Reactors: A Deterministic Model for Composable Reactive SystemsCyber Physical Systems. Model-Based Design10.1007/978-3-030-41131-2_4(59-85)Online publication date: 18-Feb-2020
https://doi.org/10.1007/978-3-030-41131-2_4
Karatkevich A(2015)Petri Nets in Design of Control AlgorithmsDesign of Reconfigurable Logic Controllers10.1007/978-3-319-26725-8_1(1-14)Online publication date: 24-Dec-2015
https://doi.org/10.1007/978-3-319-26725-8_1
Show More Cited By

Index Terms

An efficient implementation of reactivity for modeling hardware in the scenic design environment

Recommendations

Efficient implementation of QRD-RLS algorithm using hardware-software co-design
IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing

This paper presents the implementation of QR Decomposition based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA) using hardware-software co-design. The system has been implemented on Xilinx Spartan 3E FPGA with ...
Efficient FPGA hardware development: A multi-language approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of ...
Efficient Implementation of Elliptic Curve Cryptosystems on an ARM7 with Hardware Accelerator
ISC '01: Proceedings of the 4th International Conference on Information Security

This paper presents an efficient implementation of elliptic curve cryptosystems over a prime field on ARM7 with the help of a hardware accelerator. The hardware accelerator has two dedicated large number arithmetic units (LNAU's). Three different ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Copyright © 1997 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC97

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

Acceptance Rates

DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

54
Total Citations
View Citations
104
Total Downloads

Downloads (Last 12 months)34
Downloads (Last 6 weeks)8

Reflects downloads up to 06 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Kogel T(2022)Virtual Prototyping of Processor-Based PlatformsHandbook of Computer Architecture10.1007/978-981-15-6401-7_44-1(1-41)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_44-1
Lohstroh MRomeo ÍGoens ADerler PCastrillon JLee ESangiovanni-Vincentelli A(2020)Reactors: A Deterministic Model for Composable Reactive SystemsCyber Physical Systems. Model-Based Design10.1007/978-3-030-41131-2_4(59-85)Online publication date: 18-Feb-2020
https://doi.org/10.1007/978-3-030-41131-2_4
Karatkevich A(2015)Petri Nets in Design of Control AlgorithmsDesign of Reconfigurable Logic Controllers10.1007/978-3-319-26725-8_1(1-14)Online publication date: 24-Dec-2015
https://doi.org/10.1007/978-3-319-26725-8_1
Al-Akhras STahar SNicolescu GLangevin MPaulin P(2013)On the Verification of a WiMax Design Using Symbolic SimulationElectronic Proceedings in Theoretical Computer Science10.4204/EPTCS.122.3122(23-37)Online publication date: 30-Jul-2013
https://doi.org/10.4204/EPTCS.122.3
King MDave NArvind (2012)Automatic generation of hardware/software interfacesACM SIGPLAN Notices10.1145/2248487.215101147:4(325-336)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2248487.2151011
King MDave NArvind (2012)Automatic generation of hardware/software interfacesACM SIGARCH Computer Architecture News10.1145/2189750.215101140:1(325-336)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2189750.2151011
King MDave NArvind Harris TScott M(2012)Automatic generation of hardware/software interfacesProceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems10.1145/2150976.2151011(325-336)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2150976.2151011
Lee ELiu XNeuendorffer S(2009)Classes and inheritance in actor-oriented designACM Transactions on Embedded Computing Systems10.1145/1550987.15509928:4(1-26)Online publication date: 24-Jul-2009
https://dl.acm.org/doi/10.1145/1550987.1550992
Doucet FShyamasundar RKrüger IJoshi SGupta R(2007)Reactivity in systemC transaction-level modelsProceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing10.5555/1787497.1787507(34-50)Online publication date: 23-Oct-2007
https://dl.acm.org/doi/10.5555/1787497.1787507
Kundu SLerner SGupta RGielen G(2007)Automated refinement checking of concurrent systemsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326139(318-325)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326139
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents