short-paper

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems

Authors:

Michail Mavropoulos,

Georgios Keramidas,

Grigorios Adamopoulos,

Dimitris NikolosAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 161 - 166

https://doi.org/10.1145/2742060.2742091

Published: 20 May 2015 Publication History

Abstract

Processor caches play a critical role in the performance of today"s computer systems. As technology scales, due to manufacturing defects and process variations a large number of cells in a cache is expected to be faulty. The number of faulty cells varies from die to die and in the field of the application depends on the operating conditions (e.g., supply voltage, frequency). Several techniques have been proposed to tolerate faults in caches. A drawback of the redundancy based techniques is that the amount of redundancy is decided at the design time targeting a maximum number of faults, so in cases of a small number of faults (e.g., in the nominal supply voltage in a system with DVS) only a part of the redundant resources is used. In this paper we propose a new reconfigurable-self adaptive fault tolerant cache scheme. The unique characteristic of our scheme is that it uses its resources for both the reduction of the misses caused by the faulty blocks as well as for the reduction of conflict misses, depending on the number of faults, their distribution in the cache, and the running application. Our experimental results for a wide range of scientific applications and a plethora of fault maps with different SRAM failure probabilities reveal that our proposal can achieve significant benefits.

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Cited By

Mavropoulos MKeramidas GNikolos D(2022)Enabling efficient sub-block disabled caches using coarse grain spatial predictionsMicroprocessors and Microsystems10.1016/j.micpro.2022.10447990(104479)Online publication date: Apr-2022
https://doi.org/10.1016/j.micpro.2022.104479
Zhi-Bin HHua-Dong MFeng ZYi D(2016)A Fault-Tolerant L1 Cache with Predictable Performance by Virtual Filter Cache2016 13th International Conference on Embedded Software and Systems (ICESS)10.1109/ICESS.2016.31(60-66)Online publication date: Aug-2016
https://doi.org/10.1109/ICESS.2016.31

Index Terms

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems
1. Hardware
  1. Robustness
    1. Fault tolerance
      1. Redundancy

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cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 20 May 2015

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Greek national funds
European Social Fund " ESF

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GLSVLSI '15

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SIGDA

GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

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GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Mavropoulos MKeramidas GNikolos D(2022)Enabling efficient sub-block disabled caches using coarse grain spatial predictionsMicroprocessors and Microsystems10.1016/j.micpro.2022.10447990(104479)Online publication date: Apr-2022
https://doi.org/10.1016/j.micpro.2022.104479
Zhi-Bin HHua-Dong MFeng ZYi D(2016)A Fault-Tolerant L1 Cache with Predictable Performance by Virtual Filter Cache2016 13th International Conference on Embedded Software and Systems (ICESS)10.1109/ICESS.2016.31(60-66)Online publication date: Aug-2016
https://doi.org/10.1109/ICESS.2016.31

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