research-article

Performance Implications of Tolerating Cache Faults

Authors:

M. D. HillAuthors Info & Claims

IEEE Transactions on Computers, Volume 42, Issue 3

Pages 257 - 267

https://doi.org/10.1109/12.210168

Published: 01 March 1993 Publication History

Abstract

The authors investigate how much cache miss ratios increase when blocks are disabled. It is shown how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, an efficient approach is developed for calculating the exact distribution of miss ratio increases from all fault patterns, and this approach is applied to the ATUM traces. Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size and is negligible (>2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled.

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 42, Issue 3

March 1993

130 pages

ISSN:0018-9340

Issue’s Table of Contents

Copyright © Copyright © 1993 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 March 1993

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Cited By

(2017)Evaluating impact on CMPs' power for design inaccuracy diagnosisInternational Journal of Computer Applications in Technology10.1504/IJCAT.2017.08819556:3(198-209)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1504/IJCAT.2017.088195
Mavropoulos MKeramidas GAdamopoulos GNikolos DJones ALi HCoskun AMargala M(2015)ReconfigurableProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742091(161-166)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742091
Keramidas GMavropoulos MKarvouniari ANikolos DFettweis GNebel W(2014)Spatial pattern prediction based management of faulty data cachesProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616680(1-6)Online publication date: 24-Mar-2014
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Sánchez DSazeides YCebrián JGarcía JAragón J(2013)Modeling the impact of permanent faults in cachesACM Transactions on Architecture and Code Optimization10.1145/2541228.254123610:4(1-23)Online publication date: 1-Dec-2013
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Hardy DSideris ILadas NSazeides Y(2012)The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent FaultsProceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2012.14(48-59)Online publication date: 1-Dec-2012
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Abella JQuiñones ECazorla FSazeides YValero MKatevenis MMartonosi MKozyrakis CTemam O(2011)RVCProceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers10.1145/1944862.1944878(97-106)Online publication date: 24-Jan-2011
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Ndai PGoel ARoy K(2010)A scalable circuit-architecture co-design to improve memory yield for high-performance processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202262818:8(1209-1219)Online publication date: 1-Aug-2010
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Zarandi HMiremadi S(2005)Soft error mitigation in cache memories of embedded systems by means of a protected schemeProceedings of the Second Latin-American conference on Dependable Computing10.1007/11572329_11(121-130)Online publication date: 25-Oct-2005
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