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Architecture of a VLSI instruction cache for a RISC

Authors:

David A. Patterson,

Dimitris Lioupis,

Korbin Van DykeAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 11, Issue 3

Pages 108 - 116

https://doi.org/10.1145/1067651.801645

Published: 13 June 1983 Publication History

Abstract

A cache was first used in a commercial computer in 1968,¹ and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit.

The next four sections present the four architectural ideas, followed by a section on performance evaluation of each idea. We then describe the implementation of the cache and finally summarize the results.

References

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J.S. Liptay, "Structural Aspects of the System/360 Model 85, Part II: The Cache," IBM Systems Journal7(1) pp. 15-21 (1968).

[2]

D.A. Patterson and D.R. Ditzel, "The Case for the Reduced Instruction Set Computer," Computer Architecture News8(6)pp. 25-33 (15 October 1980).

Digital Library

[3]

G. Radin, "The 801 Minicomputer," Proc. Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 39-47 (March 1-3, 1982).

Digital Library

[4]

D.A. Patterson and C.H. Séquin, "A VLSI RISC," Computer15(9) pp. 8-21 (September 1982).

[5]

J. Hennessy, N. Jouppi, F. Baskett, A. Strong, T. Gross, C. Rowen, and J. Gill, "The MIPS Machine," Proc. Compcon, (February 1982).

[6]

J.K. Foderaro, K.S. Van Dyke, and D.A. Patterson, "Running RISC's," VLSI DesignIII(5) pp. 27-32 (September/October, 1982).

[7]

A.J. Smith, "Cache Memories," Computing Surveys14(3)pp. 473-530 (September, 1982).

Digital Library

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M.G.H. Katevenis, R.W. Sherburne, D.A. Patterson, and C.H. Séquin, "The RISC II Micro-Architecture," Submitted to the VLSI 83 Conference, (August 1983).

[9]

M. Katevenis, SAMOS: a SmArt MemOry computer System (outline of first general ideas), U.C.Berkeley Internal Working Paper June 1981.

[10]

D. Morris and R.N. Ibbett, The MU-5 Computer System, Springer-Verlag, 1979.

[11]

J.E. Smith, "A Study of Branch Prediction Stratagies," Proc. Eighth International Symposium on Computer Architecture, pp. 135-148 (May 1981).

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D.R. Ditzel and D.A. Patterson, "Retrospective on High-Level Language Computer Architecture," Proc. Seventh Annual International Symposium on Computer Architecture, pp. 97-104 (May 6-8, 1980).

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P. Garrison and K.S. Van Dyke, Compact RISC, CS292R Final Report December 6, 1981.

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S. McMinn, "Semiconductor Manufacturing for VLSI Designers," VLSI DesignIII(4) (July/August 1982).

[15]

M. Hill, D. Lioupis, C. Nyberg, and T. Sippel, RISC Cache Project: Final Report on Architecture and Implementation of a VLSI Cache Chip, CS292X Final Report

Cited By

Ishihara TFallah F(2005)A cache-defect-aware code placement algorithm for improving the performance of processorsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129741(995-1001)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129741
Ishihara TFallah FRoy KTiwari V(2005)A non-uniform cache architecture for low power system designProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077690(363-368)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077690
Shirvani PMcCluskey E(1999)PADded CacheProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836546Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836546
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Index Terms

Architecture of a VLSI instruction cache for a RISC
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Very large scale integration design

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Information & Contributors

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 11, Issue 3

June 1983

413 pages

ISSN:0163-5964

DOI:10.1145/1067651

Issue’s Table of Contents

ISCA '83: Proceedings of the 10th annual international symposium on Computer architecture
June 1983
424 pages
ISBN:0897911016
DOI:10.1145/800046
Chairmen:
Harold W. Lawson,
Tilak Agerwala,
Hans H. Heilborn,
Hideo Aiso,
Lars-Erik Thorelli,
Jean Loup Baer,
Mario Tokoro

Copyright © 1983 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1983

Published in SIGARCH Volume 11, Issue 3

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Cited By

Ishihara TFallah F(2005)A cache-defect-aware code placement algorithm for improving the performance of processorsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129741(995-1001)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129741
Ishihara TFallah FRoy KTiwari V(2005)A non-uniform cache architecture for low power system designProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077690(363-368)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077690
Shirvani PMcCluskey E(1999)PADded CacheProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836546Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836546
Shirvani PMcCluskey E(1999)PADded cache: a new fault-tolerance technique for cache memoriesProceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)10.1109/VTEST.1999.766701(440-445)Online publication date: 1999
https://doi.org/10.1109/VTEST.1999.766701
Pour AHill M(1993)Performance Implications of Tolerating Cache FaultsIEEE Transactions on Computers10.1109/12.21016842:3(257-267)Online publication date: 1-Mar-1993
https://dl.acm.org/doi/10.1109/12.210168
Lazzerini B(1989)Effective VLSI Processor Architectures for HLL ComputersIEEE Micro10.1109/40.167949:1(57-65)Online publication date: 1-Jan-1989
https://dl.acm.org/doi/10.1109/40.16794
Ousterhout J(1988)Switch-level delay models for digital MOS VLSIPapers on Twenty-five years of electronic design automation10.1145/62882.62941(489-495)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62941
Kabakibo AMilutinovic V(1988)Simulation study of the impact of technology on cache memory performanceMicroprocessors & Microsystems10.1016/0141-9331(88)90129-912:5(277-285)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1016/0141-9331%2888%2990129-9
McNeley KMilutinovic V(1987)Emulating a Complex Instruction Set Computer with a Reduced Instruction Set ComputerIEEE Micro10.1109/MM.1987.3049397:1(60-72)Online publication date: 1-Jan-1987
https://dl.acm.org/doi/10.1109/MM.1987.304939
Milutinovic VFura DHelbig WLinn J(1987)Architecture/Compiler Synergism in GaAs Computer SystemsComputer10.1109/MC.1987.166356620:5(72-93)Online publication date: 1-May-1987
https://dl.acm.org/doi/10.1109/MC.1987.1663566
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