Article

A cache-defect-aware code placement algorithm for improving the performance of processors

Authors:

F. FallahAuthors Info & Claims

ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Pages 995 - 1001

Published: 31 May 2005 Publication History

Abstract

Yield improvement through exploiting fault-free sections of defective chips is a well-known technique (Koren and Singh (1990) and Stapper et al. (1980)). The idea is to partition the circuitry of a chip in a way that fault-free sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.

References

[1]

{1} I. Koren and A. D. Singh, "Fault Tolerance in VLSI Circuits", IEEE Computer, special issue in fault-tolerant sisytems, vol. 23, pp. 73-83, July 1990.

Digital Library

[2]

{2} C. H. Stapper, A. N. McLaren and M. Dreckmann, "Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product", IBM Journal of Research and Development, vo. 20, pp. 398-409, 1980.

Digital Library

[3]

{3} G. Sohi, "Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors", IEEE Trans. on Computers, vol. 38, no. 4, pp. 484-492, April 1989.

Digital Library

[4]

{4} A. F. Pour and M. D. Hill, "Performance Implications of Tolerating Cache Faults", IEEE Trans. on Computers, vol. 42, no. 3, pp. 257-267, March 1993.

Digital Library

[5]

{5} X. Luo and J. C. Muzio, "A Fault-Tolerant Multiprocessor Cache Memory", Proc. IEEE Workshop on Memory Technology, Design and Testing, pp. 52-57, August 1994.

[6]

{6} J. Montanaro, et al., "A 160 MHz, 32b 0.5W CMOS RISC Microprocessor", In Proc. of Int'l Solid-State Circuits Conference, February 1996.

[7]

{7} N. R. Saxena, et al., "Fault-Tolerant Features in the HaL Memory Management Unit", IEEE Trans. on Computers, vol. 44, no. 2, pp. 170- 179, February 1995.

Digital Library

[8]

{8} M. G. Gallup, et al., "Testability Features of the 68040", in Proc. of Int'l Test Conference, pp. 749-757, September 1990.

[9]

{9} Y. Ooi, M. Kashimura, H. Takeuchi and E. Kawamura, "Fault-Tolerant Architecture in a Cache Memory Control LSI", IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 507-514, April 1992.

[10]

{10} D. A. Patterson, et al., "Architecture of a VLSI instruction cache for a RISC", In Proc. 10th Annual Int'l Symposium on Computer Architecture, vol. 11, no. 3, pp. 108-116, June, 1983.

Digital Library

[11]

{11} P. P. Shirvani and E. J. McCluskey, "PADded Cache: A New Fault-Tolerance Technique for Cache Memories", In Proc. of 17th IEEE VLSI Test Symposium, pp. 440-445, April 1999.

Digital Library

[12]

{12} M. A. Lucente, C. H. Harris and R. M. Muir, "Memory System Reliability Improvement Through Associative Cache Redundancy", In Proc. of IEEE Custom Integrated Circuits Conference, pp. 19.6.1- 19.6.4, May 1990.

[13]

{13} H. T. Vergos and D. Nikolos, "Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache", In Proc. of Int'l Computer Performance and Dependability Symposium, pp. 326-332, April 1995.

Digital Library

[14]

{14} H. T. Vergos and D. Nikolos, "Efficient Fault Tolerant Cache Memory Design", Microprocessing and Microprogramming Journal, vol. 41, no. 2, pp. 153-169, May 1995.

Digital Library

[15]

{15} H. Hill and A. J. Smith, "Evaluating Associativity in CPU Cache", IEEE Trans. on Computers, Vol. 38, No. 12, pp. 1612-1630, December, 1989.

Digital Library

[16]

{16} S. McFarling, "Program Optimization for Instruction Caches", In Proc. of Int'l Conference on Architecture Support for Programming Languages and Operating Systems, pp. 183-191, April 1989.

Digital Library

[17]

{17} W. W. Hwu and P. P. Chang, "Achieving High Instruction Cache Performance with an Optimizing Compiler", In Proc. of ISCA, pp. 242-251, May 1989.

Digital Library

[18]

{18} H. Tomiyama and H. Yasuura, "Optimal Code Placement of Embedded Software for Instruction Caches", In Proc. of European Design and Test Conference, pp. 96-101, March, 1996.

Digital Library

[19]

{19} P. Panda, N. Dutt, and A. Nicolau, "Memory Organization for Improved Data Cache Performance in Embedded Processors", In Proc. of the 9th Int'l Symposium on System Synthesis, pp. 90-95, November 1996.

Digital Library

[20]

{20} A. H. Hashemi, D. R. Kaeli, and B. Calder, "Efficient Procedure Mapping Using Cache Line Coloring", in Proc. of Programming Language Design and Implementation, pp. 171-182, June, 1997.

Digital Library

[21]

{21} S. Ghosh, M. Martonosi, and S. Malik, "Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior", ACM Trans. on Programming Languages and Systems, vol. 21, no. 4, pp. 703-746, July, 1999.

Digital Library

[22]

{22} Motorola Inc., "PowerPC 604e RISC Microprocessor Technical Summary", 1996.

[23]

{23} IBM Microelectronics Division, "The PowerPC 440 core", 1999.

[24]

{24} S. Hill, "The ARM 10 Family of Embedded Advanced Microprocessor Cores", In Proc. of HOT-Chips 13, August 2001.

[25]

{25} K. Suzuki, T. Arai, N. Kouhei, and I. Kuroda, "V830R/AV: Embedded Multimedia Superscalar RISC Processor", IEEE Micro, vol. 18, no. 2, pp. 36-47, April 1998.

Digital Library

Cited By

Sánchez DSazeides YCebrián JGarcía JAragón J(2013)Modeling the impact of permanent faults in cachesACM Transactions on Architecture and Code Optimization10.1145/2541228.254123610:4(1-23)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2541236
Goudarzi MIshihara TNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variationProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393947(93-98)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393947
Ishihara T(2005)Energy-efficient embedded system design at 90nm and belowProceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems10.5555/1783214.1783263(452-465)Online publication date: 7-Sep-2005
https://dl.acm.org/doi/10.5555/1783214.1783263

A cache-defect-aware code placement algorithm for improving the performance of processors

Recommendations

Improving cache performance with adaptive cache topologies and deferred coherence models
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture

Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on ...
Improving l2 cache performance through stream-directed optimizations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

May 2005

1032 pages

ISBN:078039254X

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 31 May 2005

Check for updates

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Upcoming Conference

ICCAD '24

Sponsor:
sigda

IEEE/ACM International Conference on Computer-Aided Design

October 27 - 31, 2024

New York , NY , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
136
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sánchez DSazeides YCebrián JGarcía JAragón J(2013)Modeling the impact of permanent faults in cachesACM Transactions on Architecture and Code Optimization10.1145/2541228.254123610:4(1-23)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2541236
Goudarzi MIshihara TNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variationProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393947(93-98)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393947
Ishihara T(2005)Energy-efficient embedded system design at 90nm and belowProceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems10.5555/1783214.1783263(452-465)Online publication date: 7-Sep-2005
https://dl.acm.org/doi/10.5555/1783214.1783263

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents