An extensible simulator for bus- and directory-based cache coherence

One of the most important concepts that must be understood by students of parallel computer architecture is cache coherence. Processors may change the value of shared variables by writing them in their private caches. These changes must be propagated to the far reaches of the system so that writes to each location are seen in the same sequence throughout the system. Of course, this can be achieved by various protocols, depending on the size of the system and the workload. Students can gain an in-depth understanding of these protocols by simulating them. Our approach is to provide students with an abstract simulator, which can be specialized through inheritance in C++ to model many different protocols. The protocols can be divided into bus based and directory based. Either of these can be invalidation or update. Hybrid and adaptive protocols can also be simulated. Among the protocols covered are MSI, MESI, MOESI, Firefly, Dragon, and a simplified SCI protocol. It would be easy to add additional protocols by subclassing appropriate classes.