Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/2818950.2818964acmotherconferencesArticle/Chapter ViewAbstractPublication PagesmemsysConference Proceedingsconference-collections
research-article

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs

Published: 05 October 2015 Publication History
  • Get Citation Alerts
  • Abstract

    Dynamic Random Access Memories (DRAM) have a big impact on performance and contribute significantly to the total power consumption in systems ranging from mobile devices to servers. Up to half of the power consumption of future high density DRAM devices will be caused by refresh commands. Moreover, not only the refresh rate does depend on the device capacity, but it strongly depends on the temperature as well. In case of 3D integration of MPSoCs with Wide I/O DRAMs the power density and thermal dissipation are increased dramatically. Hence, in 3D-DRAM even more DRAM refresh operations are required. To master these challenges, clever DRAM refresh strategies are mandatory either on hardware or on software level using new or already available infrastructures and implementations, such as Partial Array Self Refresh (PASR) or Temperature Compensated Self Refresh (TCSR).
    In this paper, we show that for dedicated applications refresh can be disabled completely without or with negligible impact on the application performance. This is possible if it is assured that either the lifetime of the data is shorter than the currently required DRAM refresh period or if the application can tolerate bit errors to some degree in a given time window.

    References

    [1]
    S. Advani, N. Chandramoorthy, K. Swaminathan, K. Irick, Y. Cho, J. Sampson, and V. Narayanan. Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems. In Computer Design (ICCD), 2014 32nd IEEE International Conference on, pages 501--504, Oct 2014.
    [2]
    S. Baek, S. Cho, and R. Melhem. Refresh now and then. Computers, IEEE Transactions on, 63(12):3114--3126, 2014.
    [3]
    J. Bennett and S. Lanning. The netflix prize. In Proceedings of KDD cup and workshop, volume 2007, page 35, 2007.
    [4]
    B. Bhat and F. Mueller. Making DRAM Refresh Predictable. In Real-Time Systems (ECRTS), 2010 22nd Euromicro Conference on, pages 145--154, July 2010.
    [5]
    I. Bhati, M.-T. Chang, Z. Chishti, S.-L. Lu, and B. Jacob. DRAM Refresh Mechanisms, Trade-offs, and Penalties. Computers, IEEE Transactions on, PP(99):1--1, 2015.
    [6]
    I. Bhati, Z. Chishti, and B. Jacob. Coordinated Refresh: Energy Efficient Techniques for DRAM Refresh Scheduling. In Proceedings of the 2013 International Symposium on Low Power Electronics and Design, ISLPED '13, pages 205--210, Piscataway, NJ, USA, 2013. IEEE Press.
    [7]
    I. Bhati, Z. Chishti, S.-L. Lu, and B. Jacob. Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, pages 235--246. ACM, 2015.
    [8]
    N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1--7, Aug. 2011.
    [9]
    C. Brugger, A. L. Chinazzo, A. F. John, C. De Schryver, N. Wehn, A. Spitz, and K. A. Zweig. Exploiting Phase Transitions for the Efficient Sampling of the Fixed Degree Sequence Model. In Advances in Social Networks Analysis and Mining (ASONAM), 2015 IEEE/ACM International Conference on. IEEE, 2015.
    [10]
    C. Brugger, V. Grigorovici, M. Jung, C. Weis, C. D. Schryver, K. A. Zweig, and N. Wehn. A Custom Computing System for Finding Similarties in Complex Networks. In Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 262--267, Montpellier, France, July 2015.
    [11]
    K. Chandrasekar, C. Weis, Y. Li, B. Akesson, O. Naji, M. Jung, N. Wehn, and K. Goossens. DRAMPower: Open-source DRAM power & energy estimation tool.
    [12]
    K. K.-W. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, and O. Mutlu. Improving DRAM performance by parallelizing refreshes with accesses. In High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pages 356--367. IEEE, 2014.
    [13]
    Z. Cui, S. A. McKee, Z. Zha, Y. Bao, and M. Chen. DTail: A Flexible Approach to DRAM Refresh Management. In Proceedings of the 28th ACM International Conference on Supercomputing, ICS '14, pages 43--52, New York, NY, USA, 2014. ACM.
    [14]
    D. Dutoit, C. Bernard, S. Cheramy, F. Clermidy, Y. Thonnart, P. Vivet, C. Freund, V. Guerin, S. Guilhot, S. Lecomte, et al. A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC. In VLSI Technology (VLSIT), 2013 Symposium on, pages C22--C23. IEEE, 2013.
    [15]
    M. Ghosh and H.-H. Lee. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. In Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on, pages 134--145, Dec 2007.
    [16]
    C. Gimmler-Dumont and N. Wehn. A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers. submitted to ACM Transactions on Embedded Computing Systems, 2013.
    [17]
    Y.-H. Gong and S. Chung. Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-power Refresh. Computers, IEEE Transactions on, PP(99):1--1, 2015.
    [18]
    T. Hamamoto, S. Sugiura, and S. Sawada. On the retention time distribution of dynamic random access memory (DRAM). Electron Devices, IEEE Transactions on, 45(6):1300--1309, Jun 1998.
    [19]
    http://www.netflixprize.com/, last access: 2014-12-01.
    [20]
    C. Isen and L. John. ESKIMO - energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 337--346, Dec 2009.
    [21]
    M. Jung, C. Weis, N. Wehn, and K. Chandrasekar. TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. In Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '13, pages 5:1--5:6, New York, NY, USA, 2013. ACM.
    [22]
    M. Jung, C. Weis, N. Wehn, M. Sadri, and L. Benini. Optimized active and power-down mode refresh control in 3D-DRAMs. In Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on, pages 1--6, Oct 2014.
    [23]
    M. Jung, C. Weis, N. Wehn, and N. Wehn. DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework. IPSJ Transactions on System LSI Design Methodology (T-SLDM), August 2015.
    [24]
    J.-S. Kim, C. S. Oh, H. Lee, D. Lee, H.-R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, H. Park, J.-W. Ryu, K. Park, S.-K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, K. Kyung, J.-S. Choi, and Y.-H. Jun. A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, pages 496--498, Feb 2011.
    [25]
    J. Krueger, D. Donofrio, J. Shalf, M. Mohiyuddin, S. Williams, L. Oliker, and F.-J. Pfreundt. Hardware/software co-design for energy-efficient seismic modeling. In Proceedings of the 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pages 1--12, 2011.
    [26]
    J. Lim, H. Lim, and S. Kang. 3D Stacked DRAM Refresh Management with Guaranteed Data Reliability. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, PP(99):1--1, 2015.
    [27]
    C.-H. Lin, D.-Y. Shen, Y.-J. Chen, C.-L. Yang, and M. Wang. SECRET: Selective error correction for refresh energy reduction in DRAMs. In Computer Design (ICCD), 2012 IEEE 30th International Conference on, pages 67--74, Sept 2012.
    [28]
    J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu. An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms. SIGARCH Comput. Archit. News, 41(3):60--71, June 2013.
    [29]
    J. Liu, B. Jaiyen, R. Veras, and O. Mutlu. RAIDR: Retention-Aware Intelligent DRAM Refresh. In Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA '12, pages 1--12, Washington, DC, USA, 2012. IEEE Computer Society.
    [30]
    S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn. Flikker: Saving DRAM Refresh-power Through Critical Data Partitioning. SIGPLAN Not., 46(3):213--224, Mar. 2011.
    [31]
    Micron Technology Inc. 4Gb: x16, x32 Mobile LPDDR3 SDRAM. July 2013.
    [32]
    Xilinx. zC706 Evaluation Board for the Zynq-7000 XC7Z045 All Programmable Soc User Guide. April 2015.
    [33]
    Xilinx, Inc. Memory Interface Generator (MIG). http://www.xilinx.com/products/intellectual-property/mig.html, 2015, Last Access: 18.02.2015.
    [34]
    J. Meza, Q. Wu, S. Kumar, and O. Mutlu. Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field. In IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2015.
    [35]
    J. Mukundan, H. Hunter, K.-h. Kim, J. Stuecheli, and J. F. Martínez. Understanding and Mitigating Refresh Overheads in High-density DDR4 DRAM Systems. In Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA '13, pages 48--59, New York, NY, USA, 2013. ACM.
    [36]
    P. J. Nair, C.-C. Chou, and M. K. Qureshi. Refresh Pausing in DRAM Memory Systems. ACM Trans. Archit. Code Optim., 11(1):10:1--10:26, Feb. 2014.
    [37]
    K. Patel, L. Benini, E. Macii, and M. Poncino. Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. In V. Paliouras, J. Vounckx, and D. Verkest, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, volume 3728 of Lecture Notes in Computer Science, pages 466--476. Springer Berlin Heidelberg, 2005.
    [38]
    M. K. Qureshi, D.-H. Kim, S. Khan, P. J. Nair, and O. Mutlu. AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. Memory, 2(4Gb):20, 2015.
    [39]
    M. Sadri, M. Jung, C. Weis, N. Wehn, and L. Benini. Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-Wise Refresh. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pages 1--4, March 2014.
    [40]
    F. Schmoll, A. Heinig, P. Marwedel, and M. Engel. Improving the Fault Resilience of an H.264 Decoder Using Static Analysis Methods. ACM Trans. Embed. Comput. Syst., 13(1s):31:1--31:27, Dec. 2013.
    [41]
    A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D. Atienza. 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling. In Proc. of ICCAD 2010, 2010.
    [42]
    J. Stuecheli, D. Kaseridis, H. Hunter, and L. John. Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. In Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on, pages 375--384, Dec 2010.
    [43]
    V. K. Tavva, R. Kasha, and M. Mutyam. EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. ACM Trans. Archit. Code Optim., 11(3):31:1--31:26, Oct. 2014.
    [44]
    R. Venkatesan, S. Herr, and E. Rotenberg. Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. In Proc. of HPCA, 2006.
    [45]
    J. Wang, X. Dong, and Y. Xie. ProactiveDRAM: A DRAM-initiated retention management scheme. In Computer Design (ICCD), 2014 32nd IEEE International Conference on, pages 22--27, Oct 2014.
    [46]
    C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, and N. Wehn. Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs. In Proceedings of the conference on Design, Automation & Test in Europe. European Design and Automation Association, 2015.
    [47]
    T. Zhang, M. Poremba, C. Xu, G. Sun, and Y. Xie. CREAM: a Concurrent-Refresh-Aware DRAM Memory Architecture. In High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pages 368--379. IEEE, 2014.
    [48]
    D. Zhu, R. Wang, Y. Wei, and D. Qian. Reducing DRAM refreshing in an error correction manner. Science China Information Sciences, pages 1--14, 2015.

    Cited By

    View all
    • (2023)Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant WorkloadsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2022VLP0001E106.A:3(491-503)Online publication date: 1-Mar-2023
    • (2022)Computing the Similarity Estimate Using Approximate MemoryIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2021.310955910:3(1593-1604)Online publication date: 1-Jul-2022
    • (2022)Probabilistic Approximate Computing at Nanoscales: From data structures to memoriesIEEE Nanotechnology Magazine10.1109/MNANO.2021.312609216:1(16-24)Online publication date: Feb-2022
    • Show More Cited By

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Other conferences
    MEMSYS '15: Proceedings of the 2015 International Symposium on Memory Systems
    October 2015
    278 pages
    ISBN:9781450336048
    DOI:10.1145/2818950
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 05 October 2015

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. 3D-Integration
    2. Approximate Computing
    3. DRAM
    4. Refresh
    5. Reliability
    6. Retention

    Qualifiers

    • Research-article
    • Research
    • Refereed limited

    Conference

    MEMSYS '15
    MEMSYS '15: International Symposium on Memory Systems
    October 5 - 8, 2015
    DC, Washington DC, USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)27
    • Downloads (Last 6 weeks)4

    Other Metrics

    Citations

    Cited By

    View all
    • (2023)Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant WorkloadsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2022VLP0001E106.A:3(491-503)Online publication date: 1-Mar-2023
    • (2022)Computing the Similarity Estimate Using Approximate MemoryIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2021.310955910:3(1593-1604)Online publication date: 1-Jul-2022
    • (2022)Probabilistic Approximate Computing at Nanoscales: From data structures to memoriesIEEE Nanotechnology Magazine10.1109/MNANO.2021.312609216:1(16-24)Online publication date: Feb-2022
    • (2022)Hardware Level ApproximationsApproximate Computing Techniques10.1007/978-3-030-94705-7_3(43-79)Online publication date: 3-Jan-2022
    • (2021)SoftRefresh: Targeted refresh for Energy-efficient DRAM systems via Software and Operating Systems supportProceedings of the International Symposium on Memory Systems10.1145/3488423.3519323(1-6)Online publication date: 27-Sep-2021
    • (2021)SEAMSACM Transactions on Embedded Computing Systems10.1145/346687520:5(1-26)Online publication date: 29-Jul-2021
    • (2021)ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586265(751-756)Online publication date: 5-Dec-2021
    • (2020)Refresh Triggered ComputationACM Transactions on Architecture and Code Optimization10.1145/341770818:1(1-29)Online publication date: 30-Dec-2020
    • (2020)HaRMonyProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378489(575-590)Online publication date: 9-Mar-2020
    • (2020)DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00035(298-312)Online publication date: Oct-2020
    • Show More Cited By

    View Options

    Get Access

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media