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Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs

Authors:

Ankur SrivastavaAuthors Info & Claims

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

Pages 82 - 87

https://doi.org/10.1145/2934583.2934589

Published: 08 August 2016 Publication History

Abstract

Three-dimensional integration enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. A dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance.

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Cited By

Shen YSchreuders LPathania APimentel A(2023)Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power RegulationACM Transactions on Embedded Computing Systems10.1145/360804022:5s(1-26)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608040
Lu TSrivastava A(2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
https://dl.acm.org/doi/10.1145/3019610
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604

Index Terms

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware

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cover image ACM Conferences

ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

August 2016

392 pages

ISBN:9781450341851

DOI:10.1145/2934583

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 08 August 2016

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National Science Foundation

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ISLPED '16

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SIGDA

ISLPED '16: International Symposium on Low Power Electronics and Design

August 8 - 10, 2016

CA, San Francisco Airport, USA

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ISLPED '16 Paper Acceptance Rate 60 of 190 submissions, 32%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Shen YSchreuders LPathania APimentel A(2023)Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power RegulationACM Transactions on Embedded Computing Systems10.1145/360804022:5s(1-26)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608040
Lu TSrivastava A(2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
https://dl.acm.org/doi/10.1145/3019610
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604

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