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Low-Power Clock Tree Synthesis for 3D-ICs

Authors:

Ankur SrivastavaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 3

Article No.: 50, Pages 1 - 24

https://doi.org/10.1145/3019610

Published: 05 April 2017 Publication History

Abstract

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV’s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates’ insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV’s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

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Cited By

Zhao XLi WZeng ZHuang ZXie BLi XBao YNakamura YWang Y(2025)Toward Advancing 3D-ICs Physical Design: Challenges and OpportunitiesProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703135(294-301)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703135
P LA SPudi VM N(2023)A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181875(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10181875
P LA SPudi V(2023)Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS60141.2023.00074(299-303)Online publication date: 19-Nov-2023
https://doi.org/10.1109/APCCAS60141.2023.00074
Show More Cited By

Index Terms

Low-Power Clock Tree Synthesis for 3D-ICs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Clock-network synthesis
  2. Integrated circuits
    1. 3D integrated circuits

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 22, Issue 3

July 2017

440 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3062395

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2017 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 April 2017

Accepted: 01 November 2016

Revised: 01 September 2016

Received: 01 May 2016

Published in TODAES Volume 22, Issue 3

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Cited By

Zhao XLi WZeng ZHuang ZXie BLi XBao YNakamura YWang Y(2025)Toward Advancing 3D-ICs Physical Design: Challenges and OpportunitiesProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703135(294-301)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703135
P LA SPudi VM N(2023)A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181875(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10181875
P LA SPudi V(2023)Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS60141.2023.00074(299-303)Online publication date: 19-Nov-2023
https://doi.org/10.1109/APCCAS60141.2023.00074
Chi JZhu YZhu BZhao X(2022)A Charger Ripple Inhibition Strategy for Motor Train Unit Based on Compound Control2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862609(159-163)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862609
Wang HLei QYang YLiu LZhao E(2022)A Clock Tree Synthesis Scheme Based On Flexible H-tree2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862608(249-252)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862608
Radhakrishnan Nair RPothiraj SNair TCengiz K(2020)A novel power aware placement and adaptive radix tree based clock tree synthesis for 3D-integrated circuitsMicroprocessors and Microsystems10.1016/j.micpro.2020.103455(103455)Online publication date: Nov-2020
https://doi.org/10.1016/j.micpro.2020.103455
Lu TSerafy CYang ZSamal SLim SSrivastava A(2017)TSV-Based 3-D ICs: Design Methods and ToolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266660436:10(1593-1619)Online publication date: Oct-2017
https://doi.org/10.1109/TCAD.2017.2666604

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