research-article

Fast power- and slew-aware gated clock tree synthesis

Authors:

Chiu-Wing ShamAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20, Issue 11

Pages 2094 - 2103

https://doi.org/10.1109/TVLSI.2011.2168834

Published: 01 November 2012 Publication History

Abstract

Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 20, Issue 11

November 2012

230 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2012.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 November 2012

Accepted: 08 September 2011

Revised: 09 January 2011

Received: 16 August 2010

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Cited By

Sitik CLiu WTaskin BSalman EHomayoun HTaskin BMohsenin TZhao W(2019)Low Voltage Clock Tree Synthesis with Local Gate ClustersProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318004(99-104)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318004
Titus TVijayakumari V(2019)Clock node capacity minimization using lookup table based controller for ultrasound and medical imaging processorCluster Computing10.1007/s10586-017-1642-522:2(4129-4134)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s10586-017-1642-5
Ravi GLipasti M(2017)CHARSTARACM SIGARCH Computer Architecture News10.1145/3140659.308021245:2(147-160)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080212
Ravi GLipasti M(2017)CHARSTARProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080212(147-160)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080212
Lu TSrivastava A(2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
https://dl.acm.org/doi/10.1145/3019610
Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Seo HKim JKang MKim TMarculescu DLiu F(2015)Synthesis for Power-Aware Clock SpinesProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840837(126-131)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840837
Lu JChen PChang CSha LHuang DTeng CCheng C(2015)ePlaceACM Transactions on Design Automation of Electronic Systems10.1145/269987320:2(1-34)Online publication date: 2-Mar-2015
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