short-paper

Automatic Conversion of Simulink Models to SysteMoC Actor Networks

Authors:

Stefan Wildermann,

Jürgen TeichAuthors Info & Claims

SCOPES '17: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems

Pages 81 - 84

https://doi.org/10.1145/3078659.3078668

Published: 12 June 2017 Publication History

Abstract

Simulink has gained a lot of acceptance due to its intuitive through block-based algorithm design, simulation, and rapid prototyping capabilities for signal processing as well as control applications. However, automatic code generation for heterogeneous architectures is currently not supported by Simulink. In the literature, there exist automatic translation toolchains for generation of C or C++ code from Simulink models, which then are used for implementation or validation purposes. But few of them approach the generation of models that can be used in well-established Electronic System Level (ESL) design methodologies and tools. In order to address this issue, we present a methodology to extract an executable specification based on Data Flow Graphs (DFGs) from a given Simulink model. Such a specification can then be used by ESL tools to perform a Design Space Exploration (DSE) and generate code for hardware/software partitions directly from the ESL model. In a case study from signal processing, we validate the equivalence of the results of the simulation in Simulink and the results obtained by simulation of the DFG fully automatically generated from the Simulink model in the SystemC-based actor language SysteMoC.

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Cited By

Letras MFalk JTeich J(2024)Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core SystemsIEEE Access10.1109/ACCESS.2024.337507912(39748-39769)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3375079
Letras MFalk JSchwarzer TTeich J(2020)Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and MeasurementsACM Transactions on Design Automation of Electronic Systems10.1145/343181426:3(1-33)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3431814
Streit FLetras MWildermann SHackenberg BFalk JBecher ATeich J(2018)Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2018.8641736(1-8)Online publication date: Dec-2018
https://doi.org/10.1109/RECONFIG.2018.8641736
Show More Cited By

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cover image ACM Other conferences

SCOPES '17: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems

June 2017

100 pages

ISBN:9781450350396

DOI:10.1145/3078659

Editor:
Sander Stuijk
Eindhoven University of Technology, The Netherlands

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAA: European Design Automation Association
SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 June 2017

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Short-paper
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SCOPES '17

SCOPES '17: 20th International Workshop on Software and Compilers for Embedded Systems

June 12 - 13, 2017

Sankt Goar, Germany

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SCOPES '17 Paper Acceptance Rate 6 of 9 submissions, 67%;

Overall Acceptance Rate 38 of 79 submissions, 48%

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Cited By

Letras MFalk JTeich J(2024)Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core SystemsIEEE Access10.1109/ACCESS.2024.337507912(39748-39769)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3375079
Letras MFalk JSchwarzer TTeich J(2020)Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and MeasurementsACM Transactions on Design Automation of Electronic Systems10.1145/343181426:3(1-33)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3431814
Streit FLetras MWildermann SHackenberg BFalk JBecher ATeich J(2018)Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2018.8641736(1-8)Online publication date: Dec-2018
https://doi.org/10.1109/RECONFIG.2018.8641736
Streit FLetras MSchid MFalk JWildermann STeich J(2017)High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera SystemsProceedings of the 11th International Conference on Distributed Smart Cameras10.1145/3131885.3131932(174-179)Online publication date: 5-Sep-2017
https://dl.acm.org/doi/10.1145/3131885.3131932

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