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DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

Published: 12 August 2021 Publication History

Abstract

In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required processing effort, we systematically select instruction sequences that maximise error-rate. The application to a post-layout pipelined floating-point unit, which is implemented in 45 nm process technology, demonstrates the effectiveness and practicability of our PUF design. Finally, DTA-PUF requires up to 50× fewer instructions than existing software processor PUF designs, limiting processing costs and resulting in up to 26% power savings.

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cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 17, Issue 3
July 2021
483 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/3464978
  • Editor:
  • Ramesh Karri
Issue’s Table of Contents
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Publication History

Published: 12 August 2021
Accepted: 01 November 2020
Revised: 01 September 2020
Received: 01 June 2020
Published in JETC Volume 17, Issue 3

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Author Tags

  1. Device identification
  2. dynamic timing analysis
  3. FPU
  4. hardware security
  5. IoT
  6. low cost PUF
  7. pipeline
  8. resource-constrained devices
  9. software-based processor PUF
  10. timing errors

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  • Refereed

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  • UK Engineering and Physical Science Research Council (EPSRC)
  • European Commission (H2020-EU)

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