research-article

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

Authors:

Ioannis Tsiokanos,

Maire O’neill,

Georgios KarakonstantisAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 17, Issue 3

Article No.: 32, Pages 1 - 24

https://doi.org/10.1145/3434281

Published: 12 August 2021 Publication History

Abstract

In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required processing effort, we systematically select instruction sequences that maximise error-rate. The application to a post-layout pipelined floating-point unit, which is implemented in 45 nm process technology, demonstrates the effectiveness and practicability of our PUF design. Finally, DTA-PUF requires up to 50× fewer instructions than existing software processor PUF designs, limiting processing costs and resulting in up to 26% power savings.

References

[1]

IEEE Standard for Floating-Point Arithmetic, in IEEE Std 754-2008, vol., no., pp. 1-70, 29 Aug. 2008.

[2]

NanGate. 2011. FreePDK45 Open Cell Library. Retrieved from http://nangate.com.

[3]

International Data Corporation. 2021. Retrieved from https://www.idc.com/.

[4]

OpenRISC Community. OpenRISC 1000 architecture manual. Retrieved from https://openrisc.io/or1k.html.

[5]

J. Aarestad, P. Ortiz, D. Acharyya, and J. Plusquellic. 2013. HELP: A hardware-embedded delay PUF. IEEE Design Test 30, 2 (2013), 17–25.

[6]

M. N. Alraja, M. M. J. Farooque, and B. Khashab. 2019. The effect of security, privacy, familiarity, and trust on users’ attitudes toward the use of the IoT-based healthcare: The mediation role of risk perception. IEEE Access 7 (2019), 111341–111354.

[7]

H. Amrouch, B. Khaleghi, A. Gerstlauer, and J. Henkel. 2017. Towards aging-induced approximations. In Proceedings of the Design Automation Conference (DAC’17). 1–6.

[8]

A. Aysu and P. Schaumont. 2013. PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAs. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig’13). 1–6.

[9]

Anys Bacha and Radu Teodorescu. 2014. Using ECC feedback to guide voltage speculation in low-voltage processors. In Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’14). IEEE Computer Society, 306–318.

Digital Library

[10]

B. M. S. Bahar Talukder, B. Ray, D. Forte, and M. T. Rahman. 2019. PreLatPUF: Exploiting DRAM latency variations for generating robust device signatures. IEEE Access 7 (2019), 81106–81120.

[11]

D. H. Bailey, E. Barszcz, J. T. Barton, D. S. Browning, R. L. Carter, L. Dagum, R. A. Fatoohi, P. O. Frederickson, T. A. Lasinski, R. S. Schreiber, H. D. Simon, V. Venkatakrishnan, and S. K. Weeratunga. 1991. The NAS parallel benchmarks summary and preliminary results. In Proceedings of the Supercomputing Conference. 158–165.

[12]

G. Bakirtzis, B. J. Simon, A. G. Collins, C. H. Fleming, and C. R. Elks. 2019. Data-driven vulnerability exploration for design phase system analysis. IEEE Syst. J. 14, 4 (2020), 4864–4873.

[13]

J. Bhasker and R. Chadha. 2009.Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer, New York, NY.

[14]

K. A. Bowman, J. W. Tschanz, S. L. Lu, P. A. Aseron, M. M. Khellah, A. Raychowdhury, B. M. Geuskens, C. Tokunaga, C. B. Wilkerson, T. Karnik, and V. K. De. 2011. A 45 nm resilient microprocessor core for dynamic variation tolerance. IEEE J. Solid-State Circ. 46, 1 (2011), 194–208.

[15]

Chun-Kai Chang, Wenqi Yin, and Mattan Erez. 2019. Assessing the impact of timing errors on HPC applications. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’19), Michela Taufer, Pavan Balaji, and Antonio J. Peña (Eds.). ACM, 70:1–70:19.

Digital Library

[16]

B. Cline, K. Chopra, D. Blaauw, and Y. Cao. 2006. Analysis and modeling of CD variation for statistical static timing. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design. 60–66.

[17]

Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, and Georgios Karakonstantis. 2016. Statistical fault injection for impact-evaluation of timing errors on application performance. In Proceedings of the Design Automation Conference (DAC’16). 13:1–13:6.

Digital Library

[18]

Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, and Andreas Burg. 2015. Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. In Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition (DATE’15), Wolfgang Nebel and David Atienza (Eds.). ACM, 381–386.

[19]

Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, and Alok Choudhary. 2007. Mitigating the effects of process variations: Architectural approaches for improving batch performance. In Proceedings of the Workshop on Architectural Support for Gigascale Integration (ASGI), San Diego, CA.

[20]

J. Delvaux and I. Verbauwhede. 2013. Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise. In Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’13). 137–142.

[21]

S. Dighe, S. R. Vangal, P. Aseron, S. Kumar, T. Jacob, K. A. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V. K. De, and S. Borkar. 2011. Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core TeraFLOPS processor. IEEE J. Solid-State Circ. 46, 1 (2011), 184–193.

[22]

R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. 2010. Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits. Proc. IEEE 98, 2 (2010), 253–266.

[23]

Anh Nguyen Duc, Ronald Jabangwe, Pangkaj Paul, and Pekka Abrahamsson. 2017. Security challenges in IoT development: A software engineering perspective. In Proceedings of the XP Scientific Workshops (XP’17). Association for Computing Machinery, New York, NY, Article 11, 5 pages.

Digital Library

[24]

Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, and Doug Burger. 2012. Architecture support for disciplined approximate programming. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12), Tim Harris and Michael L. Scott (Eds.). ACM, 301–312.

Digital Library

[25]

W. Yan F. Tehranipoor, N. Karimian and J. A. Chandy. 2017. DRAM-based intrinsic physically unclonable functions for system-level security and authentication. IEEE TVLSI 25, 3 (2017), 1085–1097.

[26]

S. Ganapathy, A. Teman, R. Giterman, A. Burg, and G. Karakonstantis. 2015. Approximate computing with unreliable dynamic memories. In Proceedings of the IEEE 13th International New Circuits and Systems Conference (NEWCAS’15). 1–4.

[27]

Fatemeh Ganji, Shahin Tajik, Fabian Fäßler, and Jean-Pierre Seifert. 2016. Strong machine learning attack against PUFs with no mathematical model. In Proceedings of the Cryptographic Hardware and Embedded Systems (CHES’16) (Lecture Notes in Computer Science), Vol. 9813. Springer, 391–411.

Digital Library

[28]

Fatemeh Ganji, Shahin Tajik, and Jean-Pierre Seifert. 2016. PAC learning of arbiter PUFs. J. Cryptogr. Eng. 6, 3 (2016), 249–258.

[29]

M. Gao, Q. Wang, M. T. Arafin, Y. Lyu, and G. Qu. 2017. Approximate computing for low power and security in the Internet of Things. Computer 50, 6 (2017), 27–34.

Digital Library

[30]

D. Garyfallou, I. Tsiokanos, N. Evmorfopoulos, G. Stamoulis, and G. Karakonstantis. 2020. Accurate estimation of dynamic timing slacks using event-driven simulation. In Proceedings of the 21st International Symposium on Quality Electronic Design (ISQED’20). 225–230.

[31]

B. Gassend, D. Clarke, M. van Dijk, and S. Devadas. 2002. Silicon physical random functions. In Proceedings of the ACM Conference on Computer and Communications Security (CCS’02). 148.

[32]

Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, and Chaitali Chakrabarti. 2007. Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 199–204.

[33]

Beayna Grigorian, Nazanin Farahpour, and Glenn Reinman. 2015. BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing. In Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture (HPCA’15). IEEE Computer Society, 615–626.

[34]

Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, and Dennis Sylvester. 2013. Underdesigned and opportunistic computing in presence of hardware variability. Trans. Comput.-Aided Des. Integr. Circuits Syst. 32, 1 (2013), 8–23.

Digital Library

[35]

B. Halak, M. Zwolinski, and M. S. Mispan. 2016. Overview of PUF-based hardware security solutions for the internet of things. In Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS’16). 1–4.

[36]

T. Hiramoto, K. Takeuchi, T. Mizutani, A. Ueda, T. Saraya, M. Kobayashi, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, and Y. Yamaguchi. 2016. Ultra-low-power and ultra-low-voltage devices and circuits for IoT applications. In Proceedings of the IEEE Silicon Nanoelectronics Workshop (SNW’16). 146–147.

[37]

Giang Hoang, Robby Bruce Findler, and Russ Joseph. 2011. Exploring circuit timing-aware language and compilation. In Proceedings of the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’11). ACM, 345–356.

Digital Library

[38]

D. E. Holcomb, W. P. Burleson, and K. Fu. 2009. Power-Up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. (Sep. 2009).

Digital Library

[39]

M. Jagielski, A. Oprea, B. Biggio, C. Liu, C. Nita-Rotaru, and B. Li. 2018. Manipulating machine learning: Poisoning attacks and countermeasures for regression learning. In Proceedings of the IEEE Symposium on Security and Privacy (SP’18). 19–35.

[40]

X. Jiao, A. Rahimi, Y. Jiang, J. Wang, H. Fatemi, J. P. de Gyvez, and R. K. Gupta. 2018. CLIM: A cross-level workload-aware timing error prediction model for functional units. IEEE Trans. Comput. 67, 6 (2018), 771–783.

[41]

Georgios Karakonstantis, Abhijit Chatterjee, and Kaushik Roy. 2011. Containing the nanometer “pandora-box”: Cross-layer design techniques for variation aware low-power systems. IEEE J. Emerg. Sel. Topics Circ. Syst. 1, 1 (2011), 19–29.

[42]

G. Karakonstantis and K. Roy. 2011. Voltage over-scaling: A cross-layer design perspective for energy efficient systems. In Proceedings of the 20th European Conference on Circuit Theory and Design (ECCTD’11). 548–551.

[43]

J. Kong and F. Koushanfar. 2014. Processor-based strong physical unclonable functions with aging-based response tuning. IEEE Trans. Emerg. Topics Comput. 2, 1 (Mar. 2014), 16–29.

[44]

J. Kong, F. Koushanfar, P. K. Pendyala, A. Sadeghi, and C. Wachsmann. 2014. PUFatt: Embedded platform attestation based on novel processor-based PUFs. In Proceedings of the Design Automation Conference (DAC’14). 1–6.

[45]

N. Li, D. Liu, and S. Nepal. 2017. Lightweight mutual authentication for IoT and its applications. IEEE Trans. Sustain. Comput. 2, 4 (2017), 359–370.

[46]

W. Liu, C. Gu, M. O’Neill, G. Qu, P. Montuschi, and F. Lombardi. 2020. Security in approximate computing and approximate computing for security: Challenges and opportunities. Proc. IEEE 108, 12 (2020), 2214–2231.

[47]

A. Maiti and P. Schaumont. 2011. Improved ring oscillator PUF: An FPGA-friendly secure primitive. J. Cryptol. 24 (2011), 375–397.

Digital Library

[48]

A. Maiti and P. Schaumont. 2012. A novel microprocessor-intrinsic Physical unclonable function. In Proceedings of the International Conference on Field Programmable Logic (FPL’12). 380–387.

[49]

J. Miskelly and M. O’Neill. 2020. Fast DRAM PUFs on commodity devices. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 39, 11 (2020), 3566–3576.

[50]

M. S. Mispan, H. Su, M. Zwolinski, and B. Halak. 2018. Cost-efficient design for modeling attacks resistant PUFs. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’18). 467–472.

[51]

Sparsh Mittal. 2016. A survey of techniques for approximate computing. ACM Comput. Surv. 48, 4 (2016), 62:1–62:33.

[52]

Lev Mukhanov, Dimitrios S. Nikolopoulos, and Bronis R. de Supinski. 2015. ALEA: Fine-grain energy profiling with basic block sampling. In Proceedings of the International Conference on Parallel Architecture and Compilation (PACT’15). IEEE Computer Society, 87–98.

[53]

G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, P. Lawthers, and S. Das. 2017. Harnessing voltage margins for energy efficiency in multicore CPUs. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’17). 503–516.

[54]

K. Parasyris, P. Koutsovasilis, V. Vassiliadis, C. D. Antonopoulos, N. Bellas, and S. Lalis. 2018. A framework for evaluating software on reduced margins hardware. In Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’18). 330–337.

[55]

Taejoon Park and Kang G. Shin. 2004. LiSP: A lightweight security protocol for wireless sensor networks. ACM Trans. Embed. Comput. Syst. 3, 3 (Aug. 2004), 634–660.

Digital Library

[56]

Md. Tauhidur Rahman, Alison Hosey, Zimu Guo, Jackson Carroll, Domenic Forte, and Mark Tehranipoor. 2017. Systematic correlation and cell neighborhood analysis of SRAM PUF for robust and unique key generation. J. Hardware Syst. Secur. 1, 2 (2017), 137–155.

[57]

A. Raychowdhury, S. Ghosh, and K. Roy. 2005. A novel on-chip delay measurement hardware for efficient speed-binning. In Proceedings of the 11th IEEE International On-Line Testing Symposium. 287–292.

[58]

J. N. Rodrigues, M. Kamuf, H. Hedberg, and V. Owall. 2005. A manual on ASIC front to back end design flow. In Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE’05). 75–76.

[59]

Ulrich Rührmair, Frank Sehnke, Jan Sölter, Gideon Dror, Srinivas Devadas, and Jürgen Schmidhuber. 2010. Modeling attacks on physical unclonable functions. In Proceedings of the ACM Computer and Communications Security Conference (CCS’10). ACM, 237–249.

[60]

Ulrich Rührmair, Xiaolin Xu, Jan Sölter, Ahmed Mahmoud, Mehrdad Majzoobi, Farinaz Koushanfar, and Wayne Burleson. 2014. Efficient power and timing side channels for physical unclonable functions. In Proceedings of the 16th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’14). Springer-Verlag, Berlin, 476–492.

Digital Library

[61]

S. Sakib, A. Milenković, M. T. Rahman, and B. Ray. 2020. An aging-resistant NAND flash memory physical unclonable function. IEEE Trans. Electron Devices 67, 3 (2020), 937–943.

[62]

J. Sartori, A. Pant, R. Kumar, and P. Gupta. 2010. Variation-aware speed binning of multi-core processors. In Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED’10). 307–314.

[63]

M. Sauer, P. Raiola, L. Feiten, B. Becker, U. RÃ¼hrmair, and I. Polian. 2017. Sensitized path PUF: A lightweight embedded physical unclonable function. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’17). 680–685.

[64]

Sophiane Senni, Lionel Torres, Gilles Sassatelli, and Abdoulaye Gamatie. 2016. Non-volatile processor based on MRAM for ultra-low-power IoT devices. J. Emerg. Technol. Comput. Syst. 13, 2, Article 17 (Dec. 2016), 23 pages.

[65]

Dimitrios N. Serpanos and Artemios G. Voyiatzis. 2013. Security challenges in embedded systems. ACM Trans. Embed. Comput. Syst. 12, 1s, Article 66 (Mar. 2013), 10 pages.

Digital Library

[66]

K. Shi, D. Boland, E. Stott, S. Bayliss, and G. A. Constantinides. 2014. Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14). 1–6.

[67]

G. E. Suh and S. Devadas. 2007. Physical unclonable functions for device authentication and secret key generation. In Proceedings of the ACM/EDAC/IEEE Design Automation Conference (DAC’07). 9–14.

[68]

K. Tovletoglou, L. Mukhanov, G. Karakonstantis, A. Chatzidimitriou, G. Papadimitriou, M. Kaliorakis, D. Gizopoulos, Z. Hadjilambrou, Y. Sazeides, A. Lampropulos, S. Das, and P. Vo. 2018. Measuring and exploiting guardbands of server-grade ARMv8 CPU cores and DRAMs. In Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’18). 6–9.

[69]

I. Tsiokanos and G. Karakonstantis. 2021. ExHero: Execution history-aware error-rate estimation in pipelined designs. IEEE Micro 41, 1 (2021), 61–68.

Digital Library

[70]

Ioannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, and Georgios Karakonstantis. 2020. DEFCON: Generating and detecting failure-prone instruction sequences via stochastic search. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’20). IEEE, 1121–1126.

[71]

I. Tsiokanos, L. Mukhanov, and G. Karakonstantis. 2019. Low-power variation-aware cores based on dynamic data-dependent bitwidth truncation. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’19). 698–703.

[72]

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, and Georgios Karakonstantis. 2018. Variation-aware pipelined cores through path shaping and dynamic cycle adjustment: Case study on a floating-point unit. In Proceedings of the International Symposium on Low-power Electronics and Design (ISLPED’18). ACM, 52:1–52:6.

Digital Library

[73]

I. Tsiokanos, L. Mukhanov, D. S. Nikolopoulos, and G. Karakonstantis. 2019. Significance-driven data truncation for preventing timing failures. IEEE TDMR 19, 1 (Mar. 2019), 25–36.

[74]

E. I. Vatajelu, G. D. Natale, M. S. Mispan, and B. Halak. 2019. On the encryption of the challenge in physically unclonable functions. In Proceedings of the IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS’19). 115–120.

[75]

I. Verbauwhede, D. Mukhopadhyay, and S. S. Roy. 2016. Embedded security. In Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems (VLSID’16). 23–23.

[76]

J. Xin and R. Joseph. 2011. Identifying and predicting timing-critical instructions to boost timing speculation. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’11). 128–139.

[77]

Yan Pan, Joonho Kong, S. Ozdemir, G. Memik, and Sung Woo Chung. 2009. Selective wordline voltage boosting for caches to manage yield under process variations. In Proceedings of the 46th ACM/IEEE Design Automation Conference. 57–62.

Digital Library

[78]

Yu Zheng, A. R. Krishna, and S. Bhunia. 2013. ScanPUF: Robust ultralow-overhead PUF using scan chain. In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC’13). 626–631.

[79]

Rafael Zalman and Albrecht Mayer. 2014. A secure but still safe and low cost automotive communication technique. In Proceedings of the 51st Annual Design Automation Conference (DAC’14). Association for Computing Machinery, New York, NY, 1–5.

Digital Library

[80]

Hang Zhang, Mateja Putic, and John Lach. 2014. Low-power GPGPU computation with imprecise hardware. In Proceedings of the 51st Annual Design Automation Conference (DAC’14). ACM, 99:1–99:6.

Digital Library

[81]

Y. Zheng, F. Zhang, and S. Bhunia. 2016. DScanPUF: A delay-based physical unclonable function built into scan chain. IEEE Trans. Very Large Scale Integr. Syst. 24, 3 (2016), 1059–1070.

Digital Library

Cited By

Yuan TWang PZhang YZhou Z(2025)An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuitIntegration10.1016/j.vlsi.2024.102319101(102319)Online publication date: Mar-2025
https://doi.org/10.1016/j.vlsi.2024.102319
Japa AMiskelly JCui YO'Neill MGu C(2024)A Novel Methodology for Processor based PUF in Approximate Computing2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558354(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558354
Yuan TWang PZhang YRen MHu S(2024)DSP-PUF: A Software PUF Based on Digital Signal Processor for IoT Security2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)10.1109/ICSICT62049.2024.10831190(1-3)Online publication date: 22-Oct-2024
https://doi.org/10.1109/ICSICT62049.2024.10831190
Show More Cited By

Index Terms

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
1. Hardware
2. Security and privacy
  1. Security in hardware
    1. Embedded systems security
    2. Hardware security implementation
      1. Hardware-based security protocols

Recommendations

Physical Unclonable Functions (PUF) for IoT Devices
Physical Unclonable Function (PUF) has recently attracted interest from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational-based approach using conventional ...
Protecting against modeling attacks: design and analysis of lightweight dynamic physical unclonable function
Abstract
The rapid integration of IoT devices has ushered in unparalleled convenience and efficiency. However, ensuring secure communication and authenticity amidst constraints such as limited resources, heterogeneous configurations, and energy efficiency ...
An Instruction Fetch Unit for a High-Performance Personal Computer

The instruction fetch unit (IFU) of the Dorado personal computer speeds up the emulation of instructions by prefetching, decoding, and preparing later instructions in parallel with the execution of earlier ones. It dispatches the machine's microcoded ...

Comments

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 17, Issue 3

July 2021

483 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3464978

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

Issue’s Table of Contents

Copyright © 2021 Copyright held by the owner/author(s). Publication rights licensed to ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 12 August 2021

Accepted: 01 November 2020

Revised: 01 September 2020

Received: 01 June 2020

Published in JETC Volume 17, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Refereed

Funding Sources

UK Engineering and Physical Science Research Council (EPSRC)
European Commission (H2020-EU)

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
189
Total Downloads

Downloads (Last 12 months)35
Downloads (Last 6 weeks)4

Reflects downloads up to 01 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Yuan TWang PZhang YZhou Z(2025)An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuitIntegration10.1016/j.vlsi.2024.102319101(102319)Online publication date: Mar-2025
https://doi.org/10.1016/j.vlsi.2024.102319
Japa AMiskelly JCui YO'Neill MGu C(2024)A Novel Methodology for Processor based PUF in Approximate Computing2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558354(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558354
Yuan TWang PZhang YRen MHu S(2024)DSP-PUF: A Software PUF Based on Digital Signal Processor for IoT Security2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)10.1109/ICSICT62049.2024.10831190(1-3)Online publication date: 22-Oct-2024
https://doi.org/10.1109/ICSICT62049.2024.10831190
Zhao XCui YLyu FGu CWang CLiu W(2024)High Reliable Processor-Based PUF on Voltage Over-Scaling Technique2024 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST63913.2024.10838392(1-6)Online publication date: 16-Dec-2024
https://doi.org/10.1109/AsianHOST63913.2024.10838392
Ran ZAbdelgawad MZhang ZCheung RYan H(2024)RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP61560.2024.00037(135-142)Online publication date: 24-Jul-2024
https://doi.org/10.1109/ASAP61560.2024.00037
Millwood OMiskelly JYang BGope PKavun ELin C(2023)PUF-Phenotype: A Robust and Noise-Resilient Approach to Aid Group-Based Authentication With DRAM-PUFs Using Machine LearningIEEE Transactions on Information Forensics and Security10.1109/TIFS.2023.326662418(2451-2465)Online publication date: 1-Jan-2023
https://dl.acm.org/doi/10.1109/TIFS.2023.3266624
Wang BCui YGu CWang CLiu W(2023)Novel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10182054(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10182054
Japa AZhang JLiu WGu C(2023)Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST59942.2023.10409381(1-6)Online publication date: 13-Dec-2023
https://doi.org/10.1109/AsianHOST59942.2023.10409381
Ni LWang PZhang YLi GDing LZhang J(2023)PI PUFComputers and Electrical Engineering10.1016/j.compeleceng.2022.108540105:COnline publication date: 1-Jan-2023
https://dl.acm.org/doi/10.1016/j.compeleceng.2022.108540

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Figures

Tables

Media

View Issue’s Table of Contents