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CARAT CAKE: replacing paging via compiler/kernel cooperation

Published: 22 February 2022 Publication History

Abstract

Virtual memory, specifically paging, is undergoing significant innovation due to being challenged by new demands from modern workloads. Recent work has demonstrated an alternative software only design that can result in simplified hardware requirements, even supporting purely physical addressing. While we have made the case for this Compiler- And Runtime-based Address Translation (CARAT) concept, its evaluation was based on a user-level prototype. We now report on incorporating CARAT into a kernel, forming Compiler- And Runtime-based Address Translation for CollAborative Kernel Environments (CARAT CAKE). In our implementation, a Linux-compatible x64 process abstraction can be based either on CARAT CAKE, or on a sophisticated paging implementation. Implementing CARAT CAKE involves kernel changes and compiler optimizations/transformations that must work on all code in the system, including kernel code. We evaluate CARAT CAKE in comparison with paging and find that CARAT CAKE is able to achieve the functionality of paging (protection, mapping, and movement properties) with minimal overhead. In turn, CARAT CAKE allows significant new benefits for systems including energy savings, larger L1 caches, and arbitrary granularity memory management.

References

[1]
[n.d.]. What is eBPF? an introduction and deep dive into the EBPF technology. https://ebpf.io/what-is-ebpf
[2]
Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen Hunt, and James Larus. 2006. Deconstructing Process Isolation. In Proceedings of the 2006 Workshop on Memory System Performance and Correctness (MSPC). 1–10.
[3]
Hanna Alam, Tianhao Zhang, Mattan Erez, and Yoav Etsion. 2017. Do-It-Yourself Virtual Memory Translation. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA 2017).
[4]
Nadav Amit. 2017. Optimizing the TLB Shootdown Algorithm with Page Access Tracking. In 2017 USENIX Annual Technical Conference (USENIX ATC 17). USENIX Association, Santa Clara, CA. 27–39. isbn:978-1-931971-38-6 https://www.usenix.org/conference/atc17/technical-sessions/presentation/amit
[5]
Sotiris Apostolakis, Ziyang Xu, Zujun Tan, Greg Chan, Simone Campanoni, and David I. August. 2020. SCAF: a speculation-aware collaborative dependence analysis framework. In Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, PLDI 2020, London, UK, June 15-20, 2020, Alastair F. Donaldson and Emina Torlak (Eds.). ACM, 638–654. https://doi.org/10.1145/3385412.3386028
[6]
Apple Corporation. 1985. Inside Macintosh. Addison-Wesley.
[7]
A. Awad, A. Basu, S. Blagodurov, Y. Solihin, and G. H. Loh. 2017. Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries. In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT). 273–287. https://doi.org/10.1109/PACT.2017.38
[8]
D. Bailey, E. Barszcz, J. Barton, D. Browning, R. Carter, L. Dagum, R. Fatoohi, S. Fineberg, P. Frederickson, T. Lasinksi, R. Schreiber, H. Simon, V. Venkatakrishnan, and S. Weeratunga. 1994. The NAS Parallel Benchmarks (NAS 1). NASA.
[9]
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark D. Hill, and Michael M. Swift. 2013. Efficient Virtual Memory for Big Memory Servers. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA 2013).
[10]
Arkaprava Basu, Mark D. Hill, and Michael M. Swift. 2012. Reducing Memory Reference Energy with Opportunistic Virtual Caching. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA ’12). 297–308.
[11]
Arkaprava Basu, Mark D. Hill, and Michael M. Swift. 2012. Reducing Memory Reference Energy with Opportunistic Virtual Caching. SIGARCH Comput. Archit. News, 40, 3 (2012), June, 297–308. issn:0163-5964 https://doi.org/10.1145/2366231.2337194
[12]
A. Bhattacharjee. 2017. Preserving Virtual Memory by Mitigating the Address Translation Wall. IEEE Micro, 37, 5 (2017), Sep., 6–10. issn:0272-1732 https://doi.org/10.1109/MM.2017.3711640
[13]
A. Bhattacharjee. 2018. Breaking the Address Translation Wall by Accelerating Memory Replays. IEEE Micro, 38, 3 (2018), May, 69–78. issn:0272-1732 https://doi.org/10.1109/MM.2018.032271063
[14]
A. Bhattacharjee, D. Lustig, and M. Martonosi. 2011. Shared last-level TLBs for chip multiprocessors. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture. 62–63. issn:2378-203X https://doi.org/10.1109/HPCA.2011.5749717
[15]
A. Bhattacharjee and M. Martonosi. 2009. Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. In 18th International Conference on Parallel Architectures and Compilation Techniques (PACT’09). 29–40. issn:1089-795X https://doi.org/10.1109/PACT.2009.26
[16]
Christian Bienia. 2011. Benchmarking Modern Multiprocessors. Ph.D. Dissertation. Princeton University.
[17]
Daniel Bittman, Peter Alvaro, Pankaj Mehra, Darrell D. E. Long, and Ethan L. Miller. 2020. Twizzler: a Data-Centric OS for Non-Volatile Memory. In 2020 USENIX Annual Technical Conference (USENIX ATC 20). USENIX Association, 65–80. isbn:978-1-939133-14-4 https://www.usenix.org/conference/atc20/presentation/bittman
[18]
Kevin Boos, Namitha Liyanage, Ramla Ijaz, and Lin Zhong. 2020. Theseus: an Experiment in Operating System Structure and State Management. In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI). 1–19.
[19]
Burroughs Corporation. 1961. The Descriptor–A definition of the B5000 Information Processing System. Burroughs Corporation, Detroit, MI. USA.
[20]
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, and David Brooks. 2014. HELIX-RC: An Architecture-compiler Co-design for Automatic Parallelization of Irregular Programs. In Proceedings of the 41st Annual International Symposium on Computer Architecuture (ISCA ’14). IEEE Press, Piscataway, NJ, USA. 217–228. isbn:978-1-4799-4394-4 http://dl.acm.org/citation.cfm?id=2665671.2665705
[21]
Miguel Castro, Manuel Costa, Jean-Philippe Martin, Marcus Peinado, Periklis Akritidis, Austin Donnelly, Paul Barham, and Richard Black. 2009. Fast byte-granularity software fault isolation. In Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles. 45–58.
[22]
David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A Theodore Markettos, J Edward Maste, Robert Norton, and Stacey Son. 2017. CHERI JNI: Sinking the Java security model into the C. ACM SIGARCH Computer Architecture News, 45, 1 (2017), 569–583.
[23]
David Chisnall, Colin Rothwell, Robert N.M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Michael Roe, Brooks Davis, and Peter G. Neumann. 2015. Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. In Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’15). Association for Computing Machinery, New York, NY, USA. 117–130. isbn:9781450328357 https://doi.org/10.1145/2694344.2694367
[24]
KDE Open Source Community. 1998. The WebKit Open Source Project. https://webkit.org/
[25]
Guilherme Cox and Abhishek Bhattacharjee. 2017. Efficient Address Translation for Architectures with Multiple Page Sizes. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).
[26]
John Criswell, Nathan Dautenhahn, and Vikram Adve. 2014. Virtual Ghost: Protecting Applications from Hostile Operating Systems. SIGARCH Comput. Archit. News, 42, 1 (2014), Feb., 81–96. issn:0163-5964 https://doi.org/10.1145/2654822.2541986
[27]
Brooks Davis, Robert NM Watson, Alexander Richardson, Peter G Neumann, Simon W Moore, John Baldwin, David Chisnall, James Clarke, Nathaniel Wesley Filardo, and Khilan Gudka. 2019. CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems. 379–393.
[28]
Gregory J. Duck and Roland H. C. Yap. 2018. EffectiveSan: Type and Memory Error Detection Using Dynamically Typed C/C++. In Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2018).
[29]
Magnus Ekman, Per Stenström, and Fredrik Dahlgren. 2002. TLB and Snoop Energy-reduction Using Virtual Caches in Low-power Chip-multiprocessors. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design (ISLPED ’02). 243–246.
[30]
Dongrui Fan, Zhimin Tang, Hailin Huang, and Guang R. Gao. 2005. An Energy Efficient TLB Design Methodology. In Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISLPED ’05). 351–356.
[31]
Nathaniel Wesley Filardo, Brett F Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, and John Baldwin. 2020. Cornucopia: Temporal safety for cheri heaps. In 2020 IEEE Symposium on Security and Privacy (SP). 608–625.
[32]
J. Gandhi, V. Karakostas, F. Ayar, A. Cristal, M. D. Hill, K. S. McKinley, M. Nemirovsky, M. M. Swift, and O. S. Ünsal. 2016. Range Translations for Fast Virtual Memory. IEEE Micro, 36, 3 (2016), May, 118–126. issn:0272-1732 https://doi.org/10.1109/MM.2016.10
[33]
[n.d.]. Native Client. https://developer.chrome.com/native-client
[34]
Andrei Gorine and Alexander Krivolapov. [n.d.]. A Kernel Mode Database System for High Performance Applications.
[35]
Kyle Hale. 2016. Hybrid Runtime Systems. Ph.D. Dissertation. Northwestern University. Available as Technical Report NWU-EECS-16-12, Department of Electrical Engineering and Computer Science, Northwestern University.
[36]
Kyle Hale and Peter Dinda. 2015. A Case for Transforming Parallel Runtimes into Operating System Kernels. In Proceedings of the 24th ACM Symposium on High-performance Parallel and Distributed Computing (HPDC 2015).
[37]
Kyle Hale and Peter Dinda. 2016. Enabling Hybrid Parallel Runtimes Through Kernel and Virtualization Support. In Proceedings of the 12th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE 2016).
[38]
Kyle Hale and Peter Dinda. 2018. An Evaluation of Asynchronous Software Events on Modern Hardware. In Proceedings of the 26th IEEE International Symposium on the Modeling, Analysis, and Simulaton of Computer and Telecommunication Systems (MASCOTS 2018).
[39]
Swapnil Haria, Mark D. Hill, and Michael M. Swift. 2018. Devirtualizing Memory in Heterogeneous Systems. In Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’18). ACM, New York, NY, USA. 637–650. isbn:978-1-4503-4911-6 https://doi.org/10.1145/3173162.3173194
[40]
Galen Hunt, Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Orion Hodson, James Larus, Steven Levi, Bjarne Steensgaard, David Tarditi, and Ted Wobber. 2007. Sealing OS Processes to Improve Dependability and Safety. In Proceedings of the 2nd ACM European Conference on Computer Systems (EuroSys). 341–354.
[41]
Galen C. Hunt and James R. Larus. 2007. Singularity: Rethinking the Software Stack. SIGOPS Operating Systems Review, 41, 2 (2007), April, 37–49.
[42]
SRI International Ian A. Mason. 2018. https://github.com/SRI-CSL/gllvm
[43]
H. Jin, M. Frumkin, and J. Yan. 1999. The Open MP Implementation of NAS Parallel Benchmarks and Its Performance (NAS 3). NASA.
[44]
Nick P. Johnson, Jordan Fix, Stephen R. Beard, Taewook Oh, Thomas B. Jablin, and David I. August. 2017. A Collaborative Dependence Analysis Framework. In Proceedings of the 2017 International Symposium on Code Generation and Optimization (CGO ’17). IEEE Press, Piscataway, NJ, USA. 148–159. isbn:978-1-5090-4931-8 http://dl.acm.org/citation.cfm?id=3049832.3049849
[45]
Toni Juan, Tomas Lang, and Juan J. Navarro. 1997. Reducing TLB Power Requirements. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED ’97). 196–201.
[46]
I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, and G. Chen. 2002. Generating physical addresses directly for saving instruction TLB energy. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 185–196.
[47]
I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, and G. Chen. 2002. Generating Physical Addresses Directly for Saving Instruction TLB Energy. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO 35). 185–196.
[48]
Vasileios Karakostas, Jayneel Gandhi, Adrian Cristal, Mark Hill, Kathryn McKinley, Mario Nemirovsky, Michael Swift, and Osman Unsal. 2016. Energy-efficient address translation. In IEEE International Symposium on High Performance Computer Architecture (HPCA). 631–643.
[49]
George Kastrinis, George Balatsouras, Kostas Ferles, Nefeli Prokopaki-Kostopoulou, and Yannis Smaragdakis. 2018. An efficient data structure for must-alias analysis. In Proceedings of the 27th International Conference on Compiler Construction. 48–58.
[50]
T. Kilburn, D. B. G. Edwards, M. J. Lanigan, and F. H. Sumner. 1962. One-Level Storage System. April.
[51]
Kenneth C. Knowlton. 1965. A Fast Storage Allocator. Commun. ACM, 8, 10 (1965), Oct., 623–624. issn:0001-0782 https://doi.org/10.1145/365628.365655
[52]
Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre Attacks: Exploiting Speculative Execution. In 40th IEEE Symposium on Security and Privacy (S&P’19).
[53]
Chris Lattner and Vikram Adve. 2004. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO’04). Palo Alto, California.
[54]
David Leopoldseder, Lukas Stadler, Thomas Würthinger, Josef Eisl, Doug Simon, and Hanspeter Mössenböck. 2018. Dominance-based duplication simulation (DBDS): code duplication to enable compiler optimizations. In Proceedings of the 2018 International Symposium on Code Generation and Optimization. 126–137.
[55]
Amit Levy, Bradford Campbell, Branden Ghena, Daniel B. Giffin, Pat Pannuto, Prabal Dutta, and Philip Levis. 2017. Multiprogramming a 64kB Computer Safely and Efficiently. In Proceedings of the 26th Symposium on Operating Systems Principles (SOSP). 234–251.
[56]
Hank Levy. 1984. Capability-Based Computer Systems. Digital Press.
[57]
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading Kernel Memory from User Space. In 27th USENIX Security Symposium (USENIX Security 18).
[58]
Jiacheng Ma, Wenyi Wang, Aaron Nelson, Michael Cuevas, Brian Homerding, Conghao Liu, Zhen Huang, Simone Campanoni, Kyle Hale, and Peter Dinda. 2021. Paths to OpenMP in the Kernel. In Proceedings of the ACM/IEEE International Conference on High Performance Computing, Networking, Storage and Analysis (SC) (Supercomputing).
[59]
Anil Madhavapeddy, Richard Mortier, Charalampos Rotsos, David Scott, Balraj Singh, Thomas Gazagnaire, Steven Smith, Steven Hand, and Jon Crowcroft. 2013. Unikernels: Library Operating Systems for the Cloud. In Proceedings of the 18^th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2013). 461–472.
[60]
A Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G Neumann, Simon W Moore, and Robert NM Watson. 2020. Position Paper: Defending Direct Memory Access with CHERI Capabilities.
[61]
Angelo Matni, Enrico Armenio Deiana, Yian Su, Lukas Gross, Souradip Ghosh, Sotiris Apostolakis, Ziyang Xu, Zujun Tan, Ishita Chaturvedi, David I. August, and Simone Campanoni. 2022. NOELLE Offers Empowering LLVM Extensions. In International Symposium on Code Generation and Optimization, 2022. CGO 2022.
[62]
Alfredo Mazzinghi, Ripduman Sohan, and Robert NM Watson. 2018. Pointer provenance in a capability architecture. In 10th $USENIX$ Workshop on the Theory and Practice of Provenance (TaPP 2018).
[63]
Kayvan Memarian, Victor BF Gomes, Brooks Davis, Stephen Kell, Alexander Richardson, Robert NM Watson, and Peter Sewell. 2019. Exploring C semantics and pointer provenance. Proceedings of the ACM on Programming Languages, 3, POPL (2019), 1–32.
[64]
Vikram Narayanan, Tianjiao Huang, David Detweiler, Dan Appel, Zhaofeng Li, Gerd Zellweger, and Anton Burtsev. 2020. RedLeaf: Isolation and Communication in a Safe Operating System. In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI). 21–39.
[65]
George Necula. 1997. Proof-carrying Code. In Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of Programming Languages (POPL 1997).
[66]
George Necula and Peter Lee. 1996. Proof-Carrying Code. School of Computer Science, Carnegie Mellon University.
[67]
George Necula and Peter Lee. 1996. Safe Kernel Extensions Without Run-time Checking. In Proceedings of the 2nd USENIX Symposium on Operating Systems Design and Implementation (OSDI 1996).
[68]
Peter G Neumann. 2018. Fundamental trustworthiness principles. New Solutions for Cybersecurity.
[69]
Omni OpenMP Compiler Group, University of Versailles Saint Quentin en Yvlines. 2014. NAS Parallel Benchmarks 3.0—Unofficial OpenMP C Version. https://github.com/benchmark-subsetting/NPB3.0-omp-C
[70]
Mark Oskin and Gabriel H. Loh. 2015. A Software-Managed Approach to Die-Stacked DRAM. In Proceedings of the 2015 International Conference on Parallel Architecture and Compilation (PACT) (PACT ’15). 188–200. isbn:978-1-4673-9524-3 https://doi.org/10.1109/PACT.2015.30
[71]
Mayank Parasar, Abhishek Bhattacharjee, and Tushar Krishna. 2018. SEESAW: Using Superpages to Improve VIPT Caches. In ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 193–206.
[72]
Charles Petzold. 1988. Programming Windows. Microsoft Press.
[73]
Kiran Puttaswamy and Gabriel H. Loh. 2006. Thermal Analysis of a 3D Die-stacked High-performance Microprocessor. In Proceedings of the 16th ACM Great Lakes Symposium on VLSI (GLSVLSI ’06). 19–24.
[74]
George Radin. 1983. The 801 Minicomputer. IBM Journal of Research and Development, 27, 3 (1983), May, 237–246. Originally published at ASPLOS I and republished in ACM SIGARCH Computer Architecture News, Volume 10, Number 2, March 1982.
[75]
Michael Rainey, Ryan Newton, Kyle Hale, Ryan Newton, Nikos Hardavellas, Simone Campanoni, Peter Dinda, and Umut Acar. 2021. Task Paralell Assembly Language for Uncompromising Parallelism. In Proceedings of the 42nd ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). to appear.
[76]
Tristan Ravitch. 2016. https://github.com/travitch/whole-program-llvm
[77]
David Sehr, Robert Muth, Cliff L Biffle, Victor Khimenko, Egor Pasko, Bennet Yee, Karl Schimpf, and Brad Chen. 2010. Adapting software fault isolation to contemporary CPU architectures.
[78]
Seunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H. Loh, Yan Solihin, Abhishek Bhattacharjee, and Arkaprava Basu. 2018. Scheduling Page Table Walks for Irregular GPU Applications. In Proceedings of the 45th Annual International Symposium on Computer Architecture (ISCA ’18). 180–192. isbn:978-1-5386-5984-7 https://doi.org/10.1109/ISCA.2018.00025
[79]
Daniel Dominic Sleator and Robert Endre Tarjan. 1985. Self-Adjusting Binary Search Trees. J. ACM, 32, 3 (1985), July, 652–686.
[80]
Avinash Sodani. 2011. Race to Exascale: Opportunities and Challenges. In Keynote at the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 44).
[81]
Brian Suchy, Simone Campanoni, Nikos Hardavellas, and Peter Dinda. 2020. CARAT: A Case for Virtual Memory through Compiler- and Runtime-Based Address Translation. In Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). 329–345.
[82]
Yulei Sui and Jingling Xue. 2016. SVF: Interprocedural Static Value-flow Analysis in LLVM. In Proceedings of the 25th International Conference on Compiler Construction (CC 2016). ACM, New York, NY, USA. 265–266. isbn:978-1-4503-4241-4 https://doi.org/10.1145/2892208.2892235
[83]
Yulei Sui and Jingling Xue. 2016. SVF: interprocedural static value-flow analysis in LLVM. In Proceedings of the 25th international conference on compiler construction. 265–266.
[84]
Ahmed Tamrawi, Hoan Anh Nguyen, Hung Viet Nguyen, and Tien N Nguyen. 2012. Build code analysis with symbolic evaluation. In Proceedings of the 34th International Conference on Software Engineering. 650–660.
[85]
Tian Tan, Yue Li, and Jingling Xue. 2016. Making k-object-sensitive pointer analysis more precise with still k-limiting. In International Static Analysis Symposium. 489–510.
[86]
Hajime Tazaki. [n.d.]. An introduction of library operating system for Linux (LibOS).
[87]
C. Villavieja, V. Karakostas, L. Vilanova, Y. Etsion, A. Ramirez, A. Mendelson, N. Navarro, A. Cristal, and O. S. Unsal. 2011. DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. In 2011 International Conference on Parallel Architectures and Compilation Techniques. 340–349. issn:1089-795X https://doi.org/10.1109/PACT.2011.65
[88]
Robert Wahbe, Steven Lucco, Thomas E. Anderson, and Susan L. Graham. 1993. Efficient Software-Based Fault Isolation. In Proceedings of the Fourteenth ACM Symposium on Operating Systems Principles (SOSP 1993).
[89]
Robert NM Watson, Robert M Norton, Jonathan Woodruff, Simon W Moore, Peter G Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, and Michael Roe. 2016. Fast protection-domain crossing in the CHERI capability-system architecture. IEEE Micro, 36, 5 (2016), 38–49.
[90]
Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert Norton, and Michael Roe. 2014. The CHERI capability model: Revisiting RISC in an age of risk. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA). 457–468. https://doi.org/10.1109/ISCA.2014.6853201
[91]
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G Neumann, Simon W Moore, and Robert NM Watson. 2019. Cherivoke: Characterising pointer revocation using cheri capabilities for temporal memory safety. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. 545–557.
[92]
Zi Yan, Daniel Lustig, David Nellans, and Abhishek Bhattacharjee. 2019. Translation Ranger: Operating System Support for Contiguity-aware TLBs. In Proceedings of the ACM/IEEE 46th International Symposium on Computer Architecture (ISCA ’19). 698–710. isbn:978-1-4503-6669-4 https://doi.org/10.1145/3307650.3322223
[93]
Zi Yan, Ján Veselý, Guilherme Cox, and Abhishek Bhattacharjee. 2017. Hardware Translation Coherence for Virtualized Systems. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA ’17). 430–443. isbn:978-1-4503-4892-8 https://doi.org/10.1145/3079856.3080211
[94]
Hongil Yoon and Gurindar S. Sohi. 2016. Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. In Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). 212–224. https://doi.org/10.1109/HPCA.2016.7446066
[95]
Hongtao Yu, Jingling Xue, Wei Huo, Xiaobing Feng, and Zhaoqing Zhang. 2010. Level by Level: Making Flow- and Context-sensitive Pointer Analysis Scalable for Millions of Lines of Code. In Proceedings of the 8th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO ’10). ACM, New York, NY, USA. 218–229. isbn:978-1-60558-635-9 https://doi.org/10.1145/1772954.1772985
[96]
Drew Zagieboylo, G. Edward Suh, and Andrew C. Myers. 2020. The Cost of Software-Based Memory Management Without Virtual Memory. CoRR, abs/2009.06789 (2020), arxiv:2009.06789. arxiv:2009.06789

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    ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
    February 2022
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