An Electromigration-Aware Wire Sizing Methodology via Particle Swarm Optimization

As semiconductor manufacturing technologies progress beyond the current 3nm, the demand for more compact and powerful VLSI circuits obliges on-chip power grid networks to become denser, resulting in a substantial increase in current densities. Consequently, Electromigration (EM) has emerged as a critical reliability concern since it can lead to voids on the metal wires and, consequently, large IR drops. In this paper, we present an EM/IR-aware wire sizing methodology based on the Particle Swarm Optimization (PSO) algorithm. Our methodology can be effectively applied to contemporary power grid networks to achieve the targeted lifetimes of the chip, and simultaneously resize the wires for area reduction. The advantage is that the proposed approach is able to deal with high-dimensional search spaces, which is imperative in our problem. Experimental results using the large-scale industrial IBM power grid benchmarks indicate that our new approach can increase the lifespan of the power grid up to 6.47 × while effectively reducing the area up to 65%.