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Power grid analysis benchmarks

Published: 21 January 2008 Publication History

Abstract

Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent experience from the placement [1] and routing [2] areas suggests that the ready availability of realistic industrial-size benchmarks can energize research in a given area, and can even lead to significant breakthroughs. To this end, we are making a number of power grid analysis benchmarks available for the public. These are all drawn from real designs, and vary over a reasonable range of size and difficulty thereby making studies of algorithm complexity possible. This paper documents the format for the various benchmarks, and give details for their access.

References

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S. N. Adya and I. L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement," Proceedings of ISPD, 2002.
[2]
G. Nam, M. Yildiz, D. Z. Pan, and P. H. Madden, "ISPD Placement Contest Updates and ISPD 2007 Global Routing Contest," Proceedings of ISPD, 2007.
[3]
R. Patel, S. Rajgopal, D. Singh, F. Baez, G. Mehta and V. Tiwari, "Reducing Power in High-Performance Microprocessors," Proceedings of DAC 1998
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J. P. Halter, and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proceedings of CICC 1997
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A. Dharchoudhury et. al., "Design and Analysis of Power Distribution Networks in PowerPC Microprocessors", Proceedings of DAC 1998
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E. Chiprout, "Fast Flip-Chip Power Grid Analysis Via Locality and Grid Shells", Proceedings of ICCAD 2004
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S. R. Nassif, and J. N. Kozhaya, "Fast Power Grid Simulation," Proceedings DAC 2000
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R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young and R. Ramaraju, "Model and analysis for combined package and on-chip power grid simulation," Proceedings of ISLPED 2000
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D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," Proceedings of DAC 2003
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H. H. Chen and D. D. Ling, "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design," Proceedings of DAC 1997
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F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI, Dec. 1994
[12]
H. Su, Y. Liu, A. Devgan, E. Acar, S. Nassif, "Full Chip Leakage Estimation Considering Power Supply and Temperature Variations," Proceedings of ISLPED 2003
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S. R. Nassif, "The Impact of Variability on Power," Proceedings ISLPED 2004
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L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, University of California, Berkeley, 1975.

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  • (2022)A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment InterconnectsProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549476(1-7)Online publication date: 30-Oct-2022
  • (2022)EI-MORProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549407(1-8)Online publication date: 30-Oct-2022
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cover image ACM Conferences
ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference
January 2008
812 pages
ISBN:9781424419227

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IEEE Computer Society Press

Washington, DC, United States

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Published: 21 January 2008

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ASP-DAC '08 Paper Acceptance Rate 122 of 350 submissions, 35%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

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  • (2024)An Electromigration-Aware Wire Sizing Methodology via Particle Swarm OptimizationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658756(403-408)Online publication date: 12-Jun-2024
  • (2022)A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment InterconnectsProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549476(1-7)Online publication date: 30-Oct-2022
  • (2022)EI-MORProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549407(1-8)Online publication date: 30-Oct-2022
  • (2020)PowerPlanningDLProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408697(1520-1525)Online publication date: 9-Mar-2020
  • (2020)Template-Based PDN Synthesis in Floorplan and Placement Using Classifier and CNN TechniquesProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045303(44-49)Online publication date: 17-Jan-2020
  • (2019)Non-Uniform Temperature Distribution in Interconnects and Its Impact on ElectromigrationProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317973(117-122)Online publication date: 13-May-2019
  • (2018)Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wiresProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201706(399-404)Online publication date: 22-Jan-2018
  • (2018)RAINProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196099(1-6)Online publication date: 24-Jun-2018
  • (2018)A Distributed Power Grid Analysis Framework from Sequential Stream GraphProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194560(183-188)Online publication date: 30-May-2018
  • (2018)Power Grid Reduction by Sparse Convex OptimizationProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178247(60-67)Online publication date: 25-Mar-2018
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