Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.5555/1266366.1266528acmconferencesArticle/Chapter ViewAbstractPublication PagesdateConference Proceedingsconference-collections
Article

A one-shot configurable-cache tuner for improved energy and performance

Published: 16 April 2007 Publication History

Abstract

We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application. Previous dynamic cache tuning approaches change the cache configuration several times as part of the tuning search process, executing the application using inferior configurations and temporarily causing energy and performance overhead. The introduced tuner uses a different approach, which non-intrusively collects data on addresses issued by the microprocessor, analyzes that data to predict the best cache configuration, and then updates the cache to the new best configuration in "one-shot," without ever having to examine inferior configurations. The result is less energy and less performance overhead, meaning that cache tuning can be applied more frequently. We show through experiments that the one-shot cache tuner can reduce memory-access related energy for instructions by 35% and comes within 4% of a previous intrusive approach, and results in 4.6 times less energy overhead and a 7.7 times speedup in tuning time compared to a previous intrusive approach, at the main expense of 12% larger size.

References

[1]
B. Agrawal, T. Sherwood. Modeling TCAM power for next generation network devices. IEEE International Symposium on Performance Analysis of Systems and Software, 2006.
[2]
D. Albonesi. Selective cache ways: on-demand cache resource allocation. MICRO 1999
[3]
ARM, www.arm.com.
[4]
Artisan. www.artisan.com
[5]
R. Balasubramonian, D. Albonesi, A. Byuktosunoglu, S. Dwarkada. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000.
[6]
E. Berg, E. Hagerstein. StatCache: a probabilistic approach to efficient and accurate data locality analysis. IEEE International Symposium on Performance Analysis of Systems and Software, 2004.
[7]
D. Burger, T. Austin, S. Bennet. Evaluating future microprocessors: the simplescalar toolset. University of Wisconsin-Madison. Computer Science Department Technical Report CS-TR-1308, July 2000
[8]
A. Ghosh, T. Givargis. Cache optimization for embedded processor cores: an analytical approach. International Conference on Computer Aided Design, November 2003.
[9]
T. Givargis. F. Vahid. Platune: a tuning framework for system-on-a-chip platforms. IEEE Transactions on Computer Aided Design, November 2002.
[10]
A. Gordon-Ross, F. Vahid, N. Dutt. Automatic tuning of two-level caches to embedded applications. Design Automation and Test in Europe, Feb 2004.
[11]
A. Gordon-Ross, F. Vahid, N. Dutt. Fast configurable-cache tuning with a unified second level cache. International Symposium on Low Power Electronics and Design, 2005.
[12]
M. Hill, A. Smith. Evaluating associativity in CPU caches, IEEE Transactions on Computing, 1989.
[13]
R. Kempke. A. McAuley. Ternary CAM memory architecture and methodology. U.S. Patent 5 841 874, Aug 13 1996
[14]
C. Lee, M. Potkonjak, W. H. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communication systems. MICRO 1997.
[15]
A. Malik, W. Moyer, D. Cermak. A low power unified cache architecture providing power and performance flexibility. International Symposium on Low Power Electronics and Design, 2000
[16]
R. Mattson, J. Gecsei, D. Slutz, I. Traiger. Evaluation techniques for storage hierarchies. IBM Systems Journal, 1970
[17]
MicroBlaze, www.xilinx.com
[18]
M. Palesi, T. Givargis, Multi-objective design space exploration using genetic algorithms. International Workshop on Hardware/Software Codesign, May 2002
[19]
J. Pierper, A. Mellan, J. Paul, D. Thomas, F. Karim. High level cache simulation for heterogeneous multiprocessors, Design Automation Conference, 2004
[20]
V. Ravikumar, R. Mahapatra, L. Bhuyan. EaseCAM: an energy and storage efficient TCAM-based router architecture for IP lookup. IEEE Transactions on Computers, May 2005.
[21]
S. Segars. Low power design techniques for microprocessors, International Solid State Circuit Conf, 2001
[22]
R. Sugumar, S. Abraham. Efficient simulation of multiple cache configurations using binomial trees. Technical Report CSE-TR-111-91, 1991.
[23]
T. Sherwood, S. Sair, B. Calder. Phase tracking and prediction. 30th International Symposium on Computer Architecture, 2003
[24]
D. Suresh, W. Najjar, F. Vahid, J. Villarreal, G. Stitt. Profiling tools for hardware/software partitioning of embedded aplications. LCTES 2003.
[25]
Synopsys, www.synopsys.com
[26]
Tensilica, Xtensa Processor Generator, www.tensilica.com/.
[27]
P. Viana. A methodology to explore the design space of memory hierarchies for embedded systems. PhD Thesis, 2006
[28]
C. Zhang, F. Vahid, W. Najjar. A highly-configurable cache architecture for embedded systems. 30th Annual International Symposium on Computer Architecture, June 2003.

Cited By

View all
  • (2016)Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded DevicesProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902987(357-360)Online publication date: 18-May-2016
  • (2013)An analytical approach for fast and accurate design space exploration of instruction cachesACM Transactions on Embedded Computing Systems10.1145/2539036.253903913:3(1-29)Online publication date: 24-Dec-2013
  • (2013)Reuse-based online models for cachesACM SIGMETRICS Performance Evaluation Review10.1145/2494232.246575641:1(279-292)Online publication date: 17-Jun-2013
  • Show More Cited By
  1. A one-shot configurable-cache tuner for improved energy and performance

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DATE '07: Proceedings of the conference on Design, automation and test in Europe
    April 2007
    1741 pages
    ISBN:9783981080124

    Sponsors

    Publisher

    EDA Consortium

    San Jose, CA, United States

    Publication History

    Published: 16 April 2007

    Check for updates

    Qualifiers

    • Article

    Conference

    DATE07
    Sponsor:
    • EDAA
    • SIGDA
    • The Russian Academy of Sciences
    DATE07: Design, Automation and Test in Europe
    April 16 - 20, 2007
    Nice, France

    Acceptance Rates

    Overall Acceptance Rate 518 of 1,794 submissions, 29%

    Upcoming Conference

    DATE '25
    Design, Automation and Test in Europe
    March 31 - April 2, 2025
    Lyon , France

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)2
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 13 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2016)Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded DevicesProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902987(357-360)Online publication date: 18-May-2016
    • (2013)An analytical approach for fast and accurate design space exploration of instruction cachesACM Transactions on Embedded Computing Systems10.1145/2539036.253903913:3(1-29)Online publication date: 24-Dec-2013
    • (2013)Reuse-based online models for cachesACM SIGMETRICS Performance Evaluation Review10.1145/2494232.246575641:1(279-292)Online publication date: 17-Jun-2013
    • (2013)A survey on cache tuning from a power/energy perspectiveACM Computing Surveys10.1145/2480741.248074945:3(1-49)Online publication date: 3-Jul-2013
    • (2013)Reuse-based online models for cachesProceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems10.1145/2465529.2465756(279-292)Online publication date: 17-Jun-2013
    • (2013)A survey and taxonomy of on-chip monitoring of multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244208818:2(1-38)Online publication date: 11-Apr-2013
    • (2013)Adaptive loop caching using lightweight runtime control flow analysisACM Transactions on Embedded Computing Systems10.1145/2435227.243525112:1s(1-23)Online publication date: 29-Mar-2013
    • (2012)Survey of scheduling techniques for addressing shared resources in multicore processorsACM Computing Surveys10.1145/2379776.237978045:1(1-28)Online publication date: 7-Dec-2012
    • (2012)Dynamic Cache Reconfiguration for Soft Real-Time SystemsACM Transactions on Embedded Computing Systems10.1145/2220336.222034011:2(1-31)Online publication date: 1-Jul-2012
    • (2011)T-SPaCSProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950904(419-424)Online publication date: 25-Jan-2011
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media