Article

Verification-guided soft error resilience

Authors:

Sanjit A. Seshia,

Subhasish MitraAuthors Info & Claims

DATE '07: Proceedings of the conference on Design, automation and test in Europe

Pages 1442 - 1447

Published: 16 April 2007 Publication History

Abstract

Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for error resilience. We demonstrate this idea of verification-guided error resilience in the context of soft errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches.

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Cited By

Gong YQian FWang L(2019)Probabilistic Evaluation of Hardware Security VulnerabilitiesACM Transactions on Design Automation of Electronic Systems10.1145/329040524:2(1-20)Online publication date: 10-Jan-2019
https://dl.acm.org/doi/10.1145/3290405
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Ebrahimi MTahoori M(2016)Invited - Cross-layer approaches for soft error modeling and mitigationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2905007(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2905007
Show More Cited By

Verification-guided soft error resilience
1. Hardware
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
  2. Software organization and properties
    1. Software functional properties
      1. Formal methods

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '07: Proceedings of the conference on Design, automation and test in Europe

April 2007

1741 pages

ISBN:9783981080124

General Chair:
Rudy Lauwereins
IMEC and KULeuven, Belgium
,
Program Chair:
Jan Madsen
DTU, Denmark

Sponsors

The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

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DATE07

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE07: Design, Automation and Test in Europe

April 16 - 20, 2007

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Gong YQian FWang L(2019)Probabilistic Evaluation of Hardware Security VulnerabilitiesACM Transactions on Design Automation of Electronic Systems10.1145/329040524:2(1-20)Online publication date: 10-Jan-2019
https://dl.acm.org/doi/10.1145/3290405
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Ebrahimi MTahoori M(2016)Invited - Cross-layer approaches for soft error modeling and mitigationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2905007(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2905007
Chen LEbrahimi MTahoori M(2016)Reliability-Aware Resource Allocation and Binding in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/283930021:2(1-27)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2839300
Chen LEbrahimi MTahoori M(2015)Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control PathsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5519-331:2(193-206)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s10836-015-5519-3
Arbel EKoyfman SKudva PMoran SChang Y(2014)Automated detection and verification of parity-protected memory elementsProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691367(1-8)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691367
Burlyaev DFradet PGirault AFettweis GNebel W(2014)Verification-guided voter minimization in triple-modular redundant circuitsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616719(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616719
Liu WWang XXu JZhang WYe YWu XNikdast MWang Z(2014)On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chipACM Journal on Emerging Technologies in Computing Systems10.1145/256492810:2(1-20)Online publication date: 6-Mar-2014
https://dl.acm.org/doi/10.1145/2564928
Georgakos GSchlichtmann USchneider RChakraborty S(2013)Reliability challenges for electric vehiclesProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488855(1-9)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488855
Clavel RPierre LLeveugle R(2011)Towards robustness analysis using PVSProceedings of the Second international conference on Interactive theorem proving10.5555/2033939.2033949(71-86)Online publication date: 22-Aug-2011
https://dl.acm.org/doi/10.5555/2033939.2033949
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