Generating pipelined datapaths using reduction techniques to shorten critical paths

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that ...

We introduce a formal system of reduction paths as a category-like structure induced from a digraph. Our motivation behind this work comes from a quantitative analysis of reduction systems based on the perspective of computational cost ...

This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed ...