Article

Native mode functional test generation for processors with applications to self test and design validation

Authors:

Jacob A. AbrahamAuthors Info & Claims

ITC '98: Proceedings of the 1998 IEEE International Test Conference

Pages 990 - 999

Published: 18 October 1998 Publication History

Abstract

New methodologies based on functional testing andbuilt-in self-test can narrow the gap betw een necessarysolutions and existing techniques for processor validation and testing. We present a versatile automatic functional test generation methodology for microprocessors.The generated assembly instruction sequences can beapplied to both design validation and manufacturingtest, especially in high speed "native" mode. All thefunctional capabilities of complex processors can be exercised, leading to high quality validation sequences andmanufacturing tests with high fault coverage. The testscan also be applied in a built-in self-test fashion. Experimental results on two microprocessors show that thismethod is very effective in generating high quality manufacturing tests as well as in functional design validation.

References

[1]

C. Montemayor et al. "Multiprocessor Design Verification for the PowerPC 620 Microprocessor," In Proc. Intl. Conf. on Computer Design, pp. 188-195, October 1995.

Digital Library

[2]

M. S. Abadir, J. Ferguson, and T. Kirkland. "Logic design verification via test generation", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, pp. 138-148, 1988.

Digital Library

[3]

D. Moundanos, J. A. Abraham, and Y. V. Hoskote. "A Unified Fraimework for Design Validation and Manufacturing Test," In Proc. Intl. Test Conf., pp. 875-884, 1996.

Digital Library

[4]

D. Brahme and J.A. Abraham. "Functional Testing of Microprocessors," IEEE Transcations on Computers, Vol. C-33, pp. 475-485, 1984.

Digital Library

[5]

S.M. Thatte arid J.A. Abraham. "Test generation for microprocessors", IEEE Transcations on Computers, Vol. C-29, pp. 429-441, 1980.

Digital Library

[6]

J. F. Franzel and P. N. Marinos. "Functional Testing of Microprocessors in a User Environment," In International Symposium on Fault-Tolerant Computing, pp. 219-224, 1984.

[7]

M.G. Lin et al. "Testing 8086," In Proc. Intl. Test Conf., pp. 426-432, 1980.

[8]

K.K. Saluja, Li Shen, and S.Y.H. Su. "A Simplified Algorithm for Testing Microprocessors," In Proc. Intl. Test Conf., pp. 668-675, 1983.

[9]

A.J. van de Goor and O. Jansen. "Self Test for the Intel 8085," Microprocessing and Microprogramming, Vol. 29, lpp. 165-175, 1990.

Digital Library

[10]

A.J. van de Goor and Th.J.W. Verhallen. "Functional Testing of Current Microprocessors (applied to the Intel i860)," In Proc. Intl. Test Conf., pp. 684-695, 1992.

Digital Library

[11]

A. Hunger and A. Gaertner. "Functional Chara-terization of microprocessors," In Proc. Intl. Test Conf., pp. 794-803, 1984.

[12]

H. Klug. "Microprocessor Testing by Instruction Sequences Derived from Random Patterns," In Proc. Intl. Test Conf., pp. 73-80, 1988.

Digital Library

[13]

P. Bottorf. "Functional Testing Folklore and Fact," In Proc. Intl. Test Conf., pp. 463-464, 1981.

[14]

G. Kildiran and P. N. Marinos. "Functional Testing of Microprocessor-like Architectures," In Proc. Intl. Test Conf., pp. 913-920, 1986.

[15]

P. Thevenod-Fosse and R. David. "Random Testing of the Data Processing Section of a Microprocessor," In International Symposium on Fault-Tolerant Computing, pp. 275-280, 1981.

[16]

P. Thevenod-fosse and R. David. "Random Testing of the Control Section of a Microprocessor," In International Symposium on Fault-Tolerant Computing, pp. 366-373, 1983.

[17]

Y. Min and S.Y.H. Su. "Testing Functional Faults in VLSI," In Proc. of the Design Automation Conf., pp. 384-392, 1982.

Digital Library

[18]

C. Lin and H. Ho. "Automatic Functional Test Program Generation for Microprocessors," In Proc. of the Design Automation Conf., pp. 605-608, 1988.

Digital Library

[19]

C. Bellon, R. Velazco, and H. Ziade. "Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits," In Proc. Intl. Test Conf., pp. 64-72, 1988.

Digital Library

[20]

J. Lee and J. Ha patel. "An Instruction sequence Assembling Methodology for Testing Microprocessors," In Proc. Intl. Test Conf., pp. 49-58, 1992.

Digital Library

[21]

W.J. Culler. "Implementing Safety Critical Systems: The VIPER microprocessor,"Kluwer Academic Publishment, 1987.

[22]

T. Nierman and J. H. Patel. "HITEC: A Test Generation Package for Sequential Circuits," In Proc. European Design and Test conference, pp. 214-218, February 1991.

Digital Library

[23]

D. G. Saab, Y. G. Saab, and J. A. Abraham. "CRIS: A Test Cultivation Program for Sequential VLSI Circuits," In Proc. Intl. Conf. on Computer-Aided Design, pp. 216-219, 1992.

Digital Library

[24]

T. Nierman, w. T. Cheng, and J. H. Patel. "PROOFS: A Fast, Memory-Efficient Seqeuential Circuit Fault Simulator," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, pp. 198-207, February 1992.

Digital Library

[25]

P.P. Gelsinger "Desingn and Test of the 80386," IEEE Design and Test of Computers, Vol. 4, pp. 42-50, June 1987.

Digital Library

[26]

C. Hinchcliff. "Simplified Microprocessor Test Generation," In Proc. Intl. Test Conf., pp. 176-180, 1982.

[27]

P.C. Maxwell, R.C. Aitken, V. Johnson, and I. Chiang. "the effect of different test sets on quality level prediction: When is 80% better than 90%?," In Proc. Intl. Test Conf., pp. 358-364, 1991.

Digital Library

[28]

J. A. Abraham and K. P. Parker. "Practical Microprocessor Testing: Open and Closed Loop Approaches," In COMPCON, pp. 308-311, 1981.

Cited By

Perez Acle JCantoro RSanchez ESonza Reorda MSquillero G(2016)Observability solutions for in-field functional test of processor-based systemsMicroprocessors & Microsystems10.1016/j.micpro.2016.09.00247:PB(392-403)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.09.002
Schlichtmann UKleeberger VAbraham JEvans AGimmler-Dumont CGlaß MHerkersdorf ANassif SWehn NFettweis GNebel W(2014)Connecting different worldsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616982(1-8)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616982
Sanchez ESquillero GTonda A(2011)Evolution of test programs exploiting a FSM processor modelProceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II10.5555/2008445.2008465(162-171)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.5555/2008445.2008465
Show More Cited By

Index Terms

Native mode functional test generation for processors with applications to self test and design validation

Index terms have been assigned to the content through auto-classification.

Recommendations

Synthesis of Native Mode Self-Test Programs
special issue on high-level test synthesis

Recent studies show that at-speed functional tests are better for finding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate ...
Native Mode Functional Self-Test Generation for Systems-on-Chip
ISQED '02: Proceedings of the 3rd International Symposium on Quality Electronic Design

With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the ...
Coverage-driven test generation for functional validation of pipelined processors

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings

ITC '98: Proceedings of the 1998 IEEE International Test Conference

October 1998

753 pages

ISBN:0780350936

Publisher

IEEE Computer Society

United States

Publication History

Published: 18 October 1998

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

42
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 29 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Perez Acle JCantoro RSanchez ESonza Reorda MSquillero G(2016)Observability solutions for in-field functional test of processor-based systemsMicroprocessors & Microsystems10.1016/j.micpro.2016.09.00247:PB(392-403)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.09.002
Schlichtmann UKleeberger VAbraham JEvans AGimmler-Dumont CGlaß MHerkersdorf ANassif SWehn NFettweis GNebel W(2014)Connecting different worldsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616982(1-8)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616982
Sanchez ESquillero GTonda A(2011)Evolution of test programs exploiting a FSM processor modelProceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II10.5555/2008445.2008465(162-171)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.5555/2008445.2008465
Mitra SSeshia SNicolici NSapatnekar S(2010)Post-silicon validation opportunities, challenges and recent advancesProceedings of the 47th Design Automation Conference10.1145/1837274.1837280(12-17)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837280
Li YMutlu OMitra SRoychowdhury J(2009)Operating system scheduling for efficient online self-test in robust systemsProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687436(201-208)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687436
Li YMakar SMitra SSciuto D(2008)CASPProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403590(885-890)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403590
Gurumurthy SVemu RAbraham JNatarajan SNarayanan VYan ZMacii EBhanja S(2008)On efficient generation of instruction sequences to test for delay defects in a processorProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366178(279-284)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366178
Lu TChen CLee KWainwright RHaddad H(2008)A hybrid software-based self-testing methodology for embedded processorProceedings of the 2008 ACM symposium on Applied computing10.1145/1363686.1364043(1528-1534)Online publication date: 16-Mar-2008
https://dl.acm.org/doi/10.1145/1363686.1364043
Lingappan LJha N(2007)Satisfiability-based automatic test program generation and design for testability for microprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89690815:5(518-530)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.896908
Kranitis NMerentitis ALaoutaris NTheodorou GPaschalis AGizopoulos DHalatsis CGielen G(2006)Optimal periodic testing of intermittent faults in embedded pipelined processor applicationsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131500(65-70)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131500
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Table of Contents