Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Authors: 
N. Julien, S. Gailhard, E. MartinAuthors Info & Claims
N. Julien, S. Gailhard, E. MartinAuthors Info & ClaimsAbstract
In modern VLSI circuits, power consumption has become a design criteria as well as speed and silicon area or gate count. To guide the designer implementing complex applications with real time constraint on dedicated circuits, we present a High Level Synthesis methodology that provides a Register Transfer Level description of an ASIC, from a behavioral description of an algorithm; this complete methodology uses basic techniques such as selection, assignment or scheduling specified for power optimization, associated with a new approach based on data format optimization. Actually, instead of the usual 32-bit floating-point format, it is power efficient to use a fixed-point format provided overflow and computation noise problems are solved. The application of our method on an usual DSP example (the DWT) shows a power reduction of more than 60%.
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- Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
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Published: 01 September 2003
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