Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay

A newly devised inductance-oscillator (iOSC) has beendeveloped which evaluates inductance impact on on-chip interconnectdelay. iOSC is a ring oscillator which is comprised of a set of wireseach with different loop inductance and accurate on-chip counter.The equivalent distance to the nearest ground grid, which serves asthe current return path, is varied to control wire inductance.A test chip using 0.13-µm node process is fabricated to demonstratethe concept of the iOSC. Four interconnect structures are implementedas imperfect coplanar waveguide, imitating clock lines orhigh-frequency inter-module signal lines. The structure with largestinductance variation measured 99 ps while a twisted ground structurewhich has small inductance variation measured 6 ps both for 3-mmwires. The experiments confirm that the inductance impact on delayhas to be adequately analyzed and controlled to estimate a timingbudget in high-speed LSI designs.